Using a OTP EPROM

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This section is currently being changed and re-written. It is very nearly finished.

Introduction

The Z88 Flash/RAM card has been working for several years now. When OZ 4.6 was introduced, allowing applications to be run in RAM, some games failed to run.

Decoder and PROM socketRAM VersionFLASH Version

This was thought to be due to an intermittent timing error from the decode chip CD74HCT139 which switches between the RAM and Flash chip but after the Z88 Hardware Investigation, it has been discovered to be a misunderstanding by both the hardware and software engineers on how to write faultlessly to the flash chip. This has only affected a few users, i.e. those who play games in RAM or who do repetitive writing to the flash card. The majority of users have not reported any problems.

Object

It has already been proved that if OZ 4.7 is run in a 256K EPROM card, the application runs faultlessly. This is because the code that the flash chip normally writes to the data bus is no longer written, as there is no flash chip. The OTP (One Time Programming) EPROM uses a similar footprint to the 512K Flash chip, so it was decided to try this combination and see if it improves the performance.

Two versions are being considered.

  • 256K - for OZ 4.7 and
    768K of RAM
  • 256K - for OZ 4.7 and
    768K of Flash

Although the best solution would be a software upgrade to OZ 4.7 allowing users to update their cards, it has been decided to see if by changing the hardware the same result may be achieved. See Writing to Flash Chips for a full explanation of what needs to be fixed. The object of this exercise is to run OZ 4.7 in the OTP EPROM in the top 256K area, leaving the rest of the address space 768K for either RAM, using the 1M RAM chip or Flash, using the 1M Flash chip. The only disadvantage is that users will no longer be able to update their OZ themselves. A socket is fitted in the card, so that the OTP EPROM may be replaced.

The address decoding will be identical for both versions.

The modified 512K/512K card has already been used with the modified extender card as described in the Z88 Hardware Investigation section, to test how the decoder chip may be used with different address maps. It was decided just to build a card using the knowledge gained from these previous tests.

Decoder Details

The same decoding algorithm is used for both cards. The output is either connected to the CE of the RAM or FLASH chip.

256K OTP EPROM, 768K FLASH or RAM


CEA19A18
256K OTP EPROM011
768K FLASH or RAM010
768K FLASH or RAM001
768K FLASH or RAM000
NOT SELECTED1XX.

Decoder Connections

The decode chip used, is repeated twice in the same device. The first device decodes the 256K EPROM with SE1, A19 and A18. The unused decoder is used to select the remainder of the address space, when the card is selected but not the 256K EPROM. The output going to either the RAM or FLASH chip enable.

Selecting the decoder outputs


I/O
PIN
No







I/O
PIN
No





FROM Z88 SE1IE110000
FROM Z88 SE1 (0)IE1510000
FROM Z88 MA19IA02X1010
FROM OTP EPROM CE (1)IA014X1010
FROM Z88 MA18IA13X1100
LOGIC 0 - 0v
IA113X1100

O

Y0

411110

O

Y0

1211110

O

Y1

511101
TO RAM or FLASH CEO

Y1

1111101

OY2611011

OY21011011
TO OTP EPROM CEOY3710111

OY3910111

Using the signal that we wish to control as the Enable signal, choosing which output is used is determined by A0 and A1. In this case they are both high, which means that Y3 is used.

  • SE1 to E (Pin 1)
  • MA19      (Pin 2) for A19 high
  • MA18      (Pin 3) for A18 high

The output for the OTP EPROM CE is Y3 (Pin 7).

The same technique is repeated for

  • SE1 to E (Pin 15)
  • From OTP EPROM CE to A0 (Pin 14) for when it is high, the OTP is not selected
  • GND to A1 (Pin 13) for logic 0

The output for the RAM or Flash is Y1 (Pin 11).

U3 Variants

U3 is currently wired up for a 512K Flash chip. There are 3 signals that use 2 different pins on the PLCC footprint.

These are displayed in the following table.

If links are to be used on a future designed board the following layout maybe considered

From edge connectorVpp (19)
A18 (37)
/PGM (22)
To U3 PLCC Footprint
Pin 1
Pin 31
512K PROM




256K PROM




512k FLASH




The 256K PROM is being used 
Vpp needs to be connected to pin 1
PGM is already connected to pin 31

PCB Modifications

Connection Chart

Edge ConDecoderSignalOTP EPROM1M RAM1M Flash
301
SE1EXISTING CONNECTION
382
A19EXISTING CONNECTION
373
A18



714OTP CE22RH 512K LKRH 512K LK


11RAM CE
RH RAM LK


11FLASH CE

LH RAM LK

256K OTP EPROM 768 RAM Modifications follows

Step

PinPinPinPinPinInstructions








Reinstate POE/ROE mods
they are no longer needed.
1

U43451415Lift up pins
DO NOT CONNECT TO PCB
2

U4126-89-1316Solder chip to board
using the remaining pins
3a

U43



A18 - Connect wire
from U4 Pin 3
to (See step 3b)
3b

U1




to a via near U1.
(Above the d in 'used'
and to the RH side of
the figure 1).

4

U47

14
Connect wire from
Pin 7, 14 to RH pad of 512K
5

U4


11

Connect to RH pad of RAM

NOTE: This is for the RAM.
It is the only difference
between the RAM
and FLASH card

6

U3




Fit socket for U3

Lift off Pin 1


U31



Connect to Vpp
Edge connector Pin 19


LK1 - LK2





256K OTP EPROM 768 FLASH Modifications follow


Step

PinPinPinPinPinInstructions








Reinstate POE/ROE mods they are no longer needed.
1

U43451415Lift up pins DO NOT CONNECT TO PCB
2

U4126-89-1316Solder chip to board using the remaining pins
3a

U43



A18 - Connect wire
from U4 Pin 3
to (See step 3b)

3b

U1




to a via near U1. (Above the d in 'used' and to the RH side of the figure 1).
4

U47

14
Connect to RH pad of 512K
5

U4


11
Connect to LH pad of RAM
6

LK1 - LK2




Cut track between LH pad of 512 and LH pad of RAM
7

U3




Fit socket for U3

DO NOT connect Pin 1 (Bottom row middle pin) to the PCB. Lift off the pin to connect the wire at the next step.

8

U31



Connect wire from the lifted off Pin 1 U3, to Vpp Edge connector Pin 19

Conclusion

Further testing will be done before reporting that a hardware solution has been found.

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