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Slot 3 and Eprom programming
The connector 21 for the top slot, slot 3, is moreover equipped to apply a programming voltage Vpp to enable an EPROM module 20 to be programmed. By means of the present invention it is possible to effect this programming directly off the address and data buses extended to the module 20 via the gate array 11 and connector 21. Slot 3 normally operates like slots 1 and 2, i.e. normal read and (if RAM is in the slot) write operations may be effected. However a bit is used in the logic array 11 as a flag to select . (OVERP in COM register) between normal operation and programming mode. When this bit is set, the circuit described below with-reference to Fig. 2 is brought into action. A separate bit is . set/reset to control the application of the programming voltage Vpp (VPP in COM register).
Features of the logic array 11 are shown in Fig. 2. A particular address range, namely the top slot, is dedicated to EPROM programming, when the flag bit mentioned above is set. When the
CPU 10 wishes to program an EPROM byte, it establishes the required address by way of the bus Ao A0 to A15 and one of the registers 15 (B0 to B7) and the required data is put on to the data bus D0 to D7.
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The logic array 11 includes a decoder 22 which detects any extended write address in the programming range (B6 = B7 = 1) and issues a signal PROGRAMA which stops the CPU clock PHI CPU, via a latch 26 and gate 28. After a delay, introduced by delay stage 23, of about 2 seconds (FRONT PORCH) a latch 27 is set, which in turn will activate the appropriate control signals to the EPROM (such as PGM, OE and CE, depending on the EPROM type). Delay duration and state of PGM, EOE, SE3 are set in EPR register.
The delay stage 24, is programmable, to accept various EPROM programming times After the delay 24, the latch 27 is reset, thus releasing the EPROM from its programming mode. A delay 25 (BACK PORCH) lasts for about 2 seconds, after which the clock to the CPU is started again. Vpp is applied throughout this sequence of operations. The delay time of the delay 24 may be programmed to allow the CPU to perform a program then verify cycle repeatedly in a training stage during which the appropriate minimum delay for secure programming of the EPROM is ascertained.
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