The Z80 CPU is driven by two Two external interrupts drive the Z80. The maskable /INT signal is used 99% of the time as the main communication channel between the Blink and the Z80 CPU for "software"-related data to drive the common hardware events such as the realtime clock, the keyboard, the serial port and battery low eventscondition. The /NMI (non-maskable interrupt) is only used for hardware connection critical events such as power failure or insertion/removal of memory cards in the external slots or the bus-connector (typically sealed of - was never used).
The /INT signal (the actual pin on the Z80 CPU) is seen as a state (enabled or disabled) between the Blink and the Z80 CPU, which is set active (low) when an interrupt signal is communicated from the Blink to the Z80, or high (when no interrupts are available)fired and until being acknowledged. The /NMI is regarded as a pulse that is fired for a hardware-related event. /NMI has not to be acknowledged.
The OZ operating system is using Z80 interrupt mode 1 for maskable interrupts, received through the RST 38H vector. The NMI interrupt is received through the RST 66H vector.
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BIT NAME Function
7 FLAPOPEN If set, flap open else flap closed
6 A19 If set, high level on A19 occurred during coma
5 FLAP If set, positive edge has occurred on FLAPOPEN
4 UART If set, an enabled UART interrupt is active
3 BTL If set, battery low pin is active
2 KEY If set, a column has gone low in snooze (or coma)
1 - -
0 TIME If set, an enabled TIME interrupt is active
UART is the result of TDRE, RDRF, DCDI and CTSI interrupt masked with UMK.
TIME is the result of TICK, SEC and MIN interrupt masked with TMK.
The logic is detailed below :
INT.UART = STA.UART = (UIT.TDRE & UMK.TDRE) | (UIT.RDRF & UMK.RDRF) | (UIT.DCDI & UMK.DCD) | (UIT.CTSI & UMK.CTS)
INT.TIME = STA.TIME = (TSTA.TICK & TMK.TICK) | (TSTA.SEC & TMK.SEC) | (TSTA.MIN & TMK.MIN)
The following diagram shows the how the registers combined defines the /INT signal (simplified):TBD. (gliffy-diagram)
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