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The original notes as supplied to Cambridge Computer were lost during the time of the company's move from Cambridge to Scotland. The following notes comes from the patent WO88/09007 (Richard MILLER and James WESTWOOD) and WO88/09573 (James WESTWOOD).
SNS
Card insertion or removal is detected by SNS. This feature was patented by James Westwood (#WO8809573, 1988-12-01)The card module slot connector is made such that during insertion or removal the SNS is shorted to ground. When SNS goes low, an NMI is fired and initiate a shutdown. This prevent any loss off data or system crash.
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Master clock is 9.83MHz for the LCD controller reading screen files in memory.
It will be appreciated that the CPU clock must be stopped and started at appropriate points in the clock cycle. In practice it may be stopped halfway through a cycle and restarted at the beginning of another cycle.
LCD controller
A 640 bits shift register is used to build the current line and shift nibbles to the LCD data lines.
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Slot 3 and Eprom programming
The The connector for the top slot, slot 3, is moreover equipped to apply a programming voltage Vpp to enable an EPROM module to be programmed. By means of the present invention it is possible to effect this programming directly off the address and data buses extended to the module via the gate array and connector. Slot 3 normally operates like slots 1 and 2, i.e. normal read and (if RAM is in the slot) write operations may be effected. However a bit is used in the logic array as a flag to select (OVERP in COM register) between normal operation and programming mode. When this bit is set, the circuit described below with-reference to Fig. 2 is brought into action. A separate bit is set/reset to control the application of the programming voltage Vpp (VPP in COM register).
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