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Display data is held in RAM within the Z88 and accessed by the gate array on a regular basis for output to the LCD. Power for the LCD is provided by a switched source, which is turned off when the machine is in the doze or coma state, thus blanking the display.
Data Output
Referring to Figure 1.2, data is output by the gate array as nibbles of LD0 - LD3 and clocked into a 640-bit shift register within the LCD by XSCL. When data for a complete row is loaded, the array generates the line purse LP which latches and displays the data and increments the row counter. This process is repeated 64 times, each row being displayed in quick succession giving the appearance of a complete display frame. At the end of each frame (ie once every 10 mS) the array reverses the logic state of the LCD frame signal FR. This prevents any electro-chemical reaction within the LCD degrading the display which would otherwise occur when, as in this case, the display is driven with dc. Figure 1.2 shows the timing for the gate array drive signals.
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