The RS232C port is controlled by registers within the gate array accessed by the CPU during I/O read/write cycles to locations with address bit 4 (A3) set to 0. Single bit latches register the state of the interface control signals RTS, CTS and DCD shift registers clocked at the selected baud rate perform the serial/parallel conversions for data transmission and reception. The physical port is presented on SK10, the conversion from RS232C levels to/from logic levels being carried out by discrete components (see Figure 1.6).
Output Circuits
Output circuits TXD and RTS, on the emitter of TR14 and TR15 respectively, switch between +SV driven by outputs from the gate array on IC4 pins 37 and 38. When the gate array outputs are at +5V (logic 1) TR14 and TR15 are turned on, switching the respective output circuit to -6V. Conversely, when the array's outputs are at OY (logic O) TR11 and TR12 are turned on, switching the respective output circuits to +5V.
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