Register Period Counts to Width in bits
TIM0 5ms 199 8
TIM1 1 second 59 6
TIM2 1 minute 255 8
TIM3 256 minutes 255 8
TIM4 64K minutes 31 5
The clock is reset to zero by settings RESTIM in the COM register. The clock will be held in reset, ie. it won't count until RESTIM is cleared again. In order to guarantee a valid result from any of these registers, software needs to read until two equal values are returned. This should always occur within three read cycles. When RESTIM is high, TIM0-TIM4 are reset.
There are three interrupts that the real time clock can generate and these are TICK (100 times a second - 10ms), SEC (once a second) and MIN (once a minute).
TSTA may never be set for all three events at once. Tick occurs on a 10ms pace when TIM0 is odd, second or minute interrupt occur when TIM0 is even (bit 0 reset). Second interrupt occurs 59 times a minute. When a minute interrupt is fired, a second interrupt has to be handled (but is not flagged in TSTA).
STA.TIME is set when TSTA.MIN or TSTA.SEC or TSTA.TICK are set according TMK mask. When all TSTA interrupts have been acknowledged, STA.TIME is reset. This logic is detailed in blink interrupts.
Three registers are associated with these interrupts:
BIT NAME Function
7 - 3 - -
2 MIN Set if minute interrupt has occurred
1 SEC Set if second interrupt has occurred
0 TICK Set if tick interrupt has occurred
BIT NAME Function
7 - 3 - -
2 MIN Set to enable minute interrupt
1 SEC Set to enable second interrupt
0 TICK Set to enable tick interrupt
BIT NAME Function
7 - 3 - -
2 MIN Set to acknowledge minute interrupt
1 SEC Set to acknowledge second interrupt
0 TICK Set to acknowledge tick interrupt