Tiny url http://tinyurl.com/jdp3qqr
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- using the NAND gates, then if that was successful, try
- a decode chip from the same family.
- Combining a Single 3-Input Positive AND-OR Gate and a single decode chip to make a high speed 74139.
The Z88 only uses one half of the dual functionality of the full chip.
Using just NAND gates requires too many of them. However using the Single 3-Input Positive AND-OR Gate and a single decode chip allows this device to be built with four 3mm high speed chips.
See http://www.neuroproductions.be/logic-lab/index.php?id=63191 for the ongoing logic in checking that the full chip will work.
NAND Gate Build
Choosing a Fast NAND gate
Looking through the datasheets for NAND gates found the following timings:-
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- A19 - Selects either the top half of the 1M memory space for the flash chip or the bottom half for the RAM.
- /CE - Selects the 1M card.
Truth Table of
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half a 74139 using two outputs
| Inputs Enable Select | Outputs | |||
|---|---|---|---|---|
| /E /CE | A1 | A0 A19 | /Y1 /CE1 FLASH | /Y0 /CE0 RAM |
| 0 | 0 | 0 | 1 | 0 |
| 0 | 0 | 1 | 0 | 1 |
| 1 | X | X | 1 | 1 |
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The Z88 only uses one half of this dual decode chip. This circuit may be made with
- 3 inverters
- 2 NAND gates
The inverters are slower than the NAND gates, so it was decided to use 5 NAND gates using 3 of the gates as inverters.
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The latest software was tried again in a standard 512K/512K Flash/RAM Card and Vic could not make the games software go wrong. The prototype board was packed and sent to Mr T who had a failing Z88 and 512K/512K Flash/RAM Card. He confirmed that it was the decoder chip that was causing the fault and suggested that another decoder could be found.
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DECODER
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Chip Build
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| Part No | Chip | Manufacture | Speed nS | Package | Price | |||
|---|---|---|---|---|---|---|---|---|
| Min | Typ | Max | ||||||
| 1741279 | SN74LVC1G139DCTR | Ti | <2.5 | SM8 | $ 0.69 | |||
| SN74LVC1G139DCUT | Ti / Farnell | <2.5 | VSSOP | £0.404 | ||||
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| View file | ||||
|---|---|---|---|---|
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This chip on its own provides the logic for the Z88 application.
Circuit Description
There are 2 inputs,
- A19 - Selects either the top half of the 1M memory space for the flash chip or the bottom half for the RAM.
- /CE - Selects the 1M card.
Truth Table of Decode Chip
| Inputs | Outputs | ||
|---|---|---|---|
| B /CE | A A19 | /Y1 /CE1 FLASH | /Y0 /CE0 RAM |
| 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 1 |
| 1 | X | 1 | 1 |
Circuit Diagram using a single decode chip.
http://tinyurl.com/h9nw253
Updated 3/10/2016
Building the circuit on a breadboard externally
Components required
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2 MSOP-8 AND 1 VSOP to IC adaptors were obtained in addition to the 5 2-to-4 Line Decoder chips.
This circuit could now be bread-boarded and tested outside the Z88 card case.
The four signal and power lines can be seen connecting the card to the breadboard.
The Games play without crashing.
Full 74139 Version Build
Adding an additional chip SN74LVC1G0832 will allow the /CE, A and B to be decoded.
Looking through the datasheets for a a Texas Instruments VC1 chip found found the following timings:-
| Part No | Chip | Manufacture | Speed nS | Package | Price | |||
|---|---|---|---|---|---|---|---|---|
| Min | Typ | Max | ||||||
SN74LVC1G0832 | Ti | <2.5 | SOT-23 (DBV) | $ 0.69 | ||||
| SN74LVC1G139DCUT | Ti / Farnell | <2.5 | VSSOP | £0.404 | ||||
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| View file | ||||
|---|---|---|---|---|
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Circuit Description
There are 2 inputs,
- A19 - Selects either the top half of the 1M memory space for the flash chip or the bottom half for the RAM.
- /CE - Selects the 1M card.
Truth Table of Decode Chip
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Logic Diagram
(to be changed)
Original
Cut Down Version using two inputs and two outputs
This ignores A1 GND line.
The Z88 only uses one half of this dual decode chip. This circuit may be made with
- 3 inverters
- 2 NAND gates
The inverters are slower than the NAND gates, so it was decided to use 5 NAND gates using 3 of the gates as inverters.
Logic Lab Test v Truth Table
The logic was checked with thanks to http://www.neuroproductions.be/logic-lab/ for the simulator.
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| Inputs Enable Select | Outputs | |||
|---|---|---|---|---|
| /E /CE | A0 A19 | /Y1 /CE1 FLASH | /Y0 /CE0 RAM | |
| 00 | 0 | 0 | 1 | 0 |
| 01 | 0 | 1 | 0 | 1 |
| 02 | 1 | X0 | 1 | 1 |
Circuit Diagram using a single decode chip.
http://tinyurl.com/h9nw253
Updated 3/10/2016
Building the circuit on a breadboard externally
Components required
...
...
2 MSOP-8 AND 1 VSOP to IC adaptors were obtained in addition to the 5 2-to-4 Line Decoder chips.
This circuit could now be bread-boarded and tested outside the Z88 card case.
The four signal and power lines can be seen connecting the card to the breadboard.
| 03 | 1 | 1 | 1 | 1 |
00
01
02
03
They both agree.
Circuit Diagram using the Single 3-Input Positive AND-OR Gate and a single decode chip.
To be drawn
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| Note | ||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
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The names of the signals on the scope are not all the same as shown in the circuit.
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Printed Circuit Board
A PCB has been laid out (just in case Tony's prototype works).(this needs to be done.)
Main points
- A letterbox slot has been made in the centre of the HD1, HD2, (which are connected both sides,) so that either direct soldering or wire links may be used to connect the signals from the 512K/512K card to the PCB.
- The pads of the footprint of the SOT-23-5 have been made longer, to enable easier soldering of the small parts.
- The bottom Left Hand corner of the PCB matches the shape of the 512K/512K Card for easy alignment.
- C2 on the 512K/512K, needs to be removed and put onto the PCB, in the same space. This is to make the PCB a bit larger for stability.
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