Tiny url http://tinyurl.com/jdp3qqr
...
The Z88 only uses one half of this dual decode chip. This circuit may be made with
- 3 inverters
- 2 NAND gates
The inverters are slower than the NAND gates, so it was decided to use 5 NAND gates using 3 of the gates as inverters.
...
| Part No | Chip | Manufacture | Speed nS | Package | Price | |||
|---|---|---|---|---|---|---|---|---|
| Min | Typ | Max | ||||||
| 1741279 | SN74LVC1G139DCTR | Ti | <2.5 | SM8 | $ 0.69 | |||
| SN74LVC1G139DCUT | Ti / Farnell | <2.5 | VSSOP | £0.404 | ||||
...
|
|
Full Data Sheet for SN74LVC1G139 2-to-4 Line Decoder
| View file | ||||
|---|---|---|---|---|
|
This chip on its own provides the logic for the Z88 application.
...
| Part No | Chip | Manufacture | Speed nS | Package | Price | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Min | Typ | Max | |||||||||||
SN74LVC1G0832 | Ti | <2.5 | SOT-23 (DBV) | $ 0.69 | SN74LVC1G139DCUT | Ti / Farnell | <2.5VSSOP | £0.404 | |||||
Single 3-Input Positive AND-OR Gate display fast times.
...
|
|
Full Data Sheet of SN74LVC1G0832DBVR
| View file | ||||
|---|---|---|---|---|
|
...
The Z88 only uses one half of this dual decode chip. This circuit may be made with
- 3 inverters
- 2 NAND gates
The inverters are slower than the NAND gates, so it was decided to use 5 NAND gates using 3 of the gates as inverters.
...
Circuit Diagram using the Single 3-Input Positive AND-OR Gate and a single decode chip.
To be drawn
...