Tiny url http://tinyurl.com/jdp3qqr
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The Z88 only uses one half of this dual decode chip. This circuit may be made with
- 3 inverters
- 2 NAND gates
The inverters are slower than the NAND gates, so it was decided to use 5 NAND gates using 3 of the gates as inverters.
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| Inputs Enable Select | Outputs | |||
|---|---|---|---|---|
| /E /CE | A0 A19 | /Y1 /CE1 FLASH | /Y0 /CE0 RAM | |
| 00 | 0 | 0 | 1 | 0 |
| 01 | 0 | 1 | 0 | 1 |
| 02 | 1 | 0 | 1 | 1 |
| 03 | 1 | 1 | 1 | 1 |
00 |
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| 01 |
...
|
02 |
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| 03 |
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|
They both agree.
Circuit Diagram
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| Part No | Chip | Manufacture | Speed nS | Package | Price | |||
|---|---|---|---|---|---|---|---|---|
| Min | Typ | Max | ||||||
| 1741279 | SN74LVC1G139DCTR | Ti | <2.5 | SM8 | $ 0.69 | |||
| SN74LVC1G139DCUT | Ti / Farnell | <2.5 | VSSOP | £0.404 | ||||
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| Part No | Chip | Manufacture | Speed nS | Package | Price | |||
|---|---|---|---|---|---|---|---|---|
| Min | Typ | Max | ||||||
SN74LVC1G0832 | Ti | <2.5 | SOT-23 (DBV) | $ 0.69 | ||||
Single 3-Input Positive AND-OR Gate display fast times.
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The Z88 only uses one half of this dual decode chip. This circuit may be made with
- 3 inverters
- 2 NAND gates
The inverters are slower than the NAND gates, so it was decided to use 5 NAND gates using 3 of the gates as inverters.
...
Circuit Diagram using the Single 3-Input Positive AND-OR Gate and a single decode chip.
To be drawn
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