Tiny url http://tinyurl.com/jdp3qqr
...
The Z88 only uses one half of this dual decode chip. This circuit may be made with
- 3 inverters
- 2 NAND gates
The inverters are slower than the NAND gates, so it was decided to use 5 NAND gates using 3 of the gates as inverters.
...
| Inputs Enable Select | Outputs | |||
|---|---|---|---|---|
| /E /CE | A0 A19 | /Y1 /CE1 FLASH | /Y0 /CE0 RAM | |
| 00 | 0 | 0 | 1 | 0 |
| 01 | 0 | 1 | 0 | 1 |
| 02 | 1 | 0 | 1 | 1 |
| 03 | 1 | 1 | 1 | 1 |
00
| 01
|
02
| 03
|
They both agree.
Circuit Diagram
...
Using 5 NAND Gates to prove that there is a hardware problem was very useful, but for a production run using a single chip to replace these is the next step.
Choosing a Decoder chip
Looking through the datasheets for a Texas Instruments VC1 chip found the following timings:-
| Part No | Chip | Manufacture | Speed nS | Package | Price | |||
|---|---|---|---|---|---|---|---|---|
| Min | Typ | Max | ||||||
| 1741279 | SN74LVC1G139DCTR | Ti | <2.5 | SM8 | $ 0.69 | |||
| SN74LVC1G139DCUT | Ti / Farnell | <2.5 | VSSOP | £0.404 | ||||
...
|
|
Full Data Sheet for SN74LVC1G139 2-to-4 Line Decoder & Timing
|
...
|
This chip on its own provides the logic for the Z88 application.
...
| Part No | Chip | Manufacture | Speed nS | Package | Price | |||
|---|---|---|---|---|---|---|---|---|
| Min | Typ | Max | ||||||
SN74LVC1G0832 | Ti | <2.5 | SOT-23 (DBV) | $ 0.69 | ||||
...
The Z88 only uses one half of this dual decode chip. This circuit may be made with
- 3 inverters
- 2 NAND gates
The inverters are slower than the NAND gates, so it was decided to use 5 NAND gates using 3 of the gates as inverters.
Logic Lab Test v Truth Table
The logic was checked against the Simplified Schematic with thanks to http://www.neuroproductions.be/logic-lab/ for the simulator.
| Inputs Enable Select | Outputs | ||||||||
|---|---|---|---|---|---|---|---|---|---|
| / | ECE | /CE A | A0BA19 | /Y3 | / | Y1Y2 | /CE1 FLASH Y1 | /Y0 /CE0 RAM | |
| 0000 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | ||
| 01 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | ||
| 02 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | ||
| 03 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | ||
| 1 | X | X | 1 | 1 | 1 | 1 | |||
00
01
02
03
They both agree.
Circuit Diagram using the Single 3-Input Positive AND-OR Gate and a single decode chip.
To be drawn
...