Tiny url http://tinyurl.com/jdp3qqr
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Some games that run in RAM, particularly when in combination with OZ v4.6 and later - running in slot 1, fails to run on the 512K/512K Flash/RAM Card. This may be has been due to a timing error which is was introduced by the decode chip CD74HCT139 which switches between the RAM and Flash chip.
Although this is one of the fastest decode chips, it is has been proved to be too slow for our purposes.
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The object of this exercise is to see if by redefining the design on a small PCB, with the same footprint of the existing decode chip, a faster decode could be achieved by
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- Using high speed NAND gates, to see if then if that was successful
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- Then try
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- using a decode chip from the same family.
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- Using the knowledge gained, add the circuit on the card to add the components to make a high speed 74139.
The Z88 only uses one half of the dual functionality of the full chip.
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Adding 3 more of these decode chips allow full functionality using four 3mm wide high speed chips.
See http://www.neuroproductions.be/logic-lab/index.php?id=63191 for the ongoing logic in checking that the full chip will work.
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The Z88 only uses one half of this dual decode chip. This circuit may be made with
- 3 inverters
- 2 NAND gates
The inverters are slower than the NAND gates, so it was decided to use 5 NAND gates using 3 of the gates as inverters.
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Choosing a Decoder chip
Looking through the datasheets data sheets for a Texas Instruments VC1 chip found the following timings:-
| Part No | Chip | Manufacture | Speed nS | Package | Price | |||
|---|---|---|---|---|---|---|---|---|
| Min | Typ | Max | ||||||
| 1741279 | SN74LVC1G139DCTR | Ti | <2.5 | SM8 | $ 0.69 | |||
| SN74LVC1G139DCUT | Ti / Farnell | <2.5 | VSSOP | £0.404 | ||||
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The Games play without crashing.
Full 74139 Version Build
Adding an additional chip SN74LVC1G139 2-to-4 Line Decoder will allow the /CE and B for /Y2 and /Y3 to be decoded.
Looking through the datasheets for a Texas Instruments VC1 chip found the following timings:-
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SN74LVC1G0832
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Here is the chip that has been chosen:-
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| PART NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| SN74LVC1G0832DBVR | SOT-23 (DBV) | 3.05 mm × 3.05 mm |
Full Data Sheet of SN74LVC1G0832DBVR
| View file | ||||
|---|---|---|---|---|
|
As the decoder chip above works and that it replaces 1/4 of the 74139, the most straightforward way of building the full version is to add 3 further chips to the design.
Logic Diagram
(to be changed)
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The Z88 only uses one half of this dual decode chip. This circuit may be made with
- 3 inverters
- 2 NAND gates
The inverters are slower than the NAND gates, so it was decided to use 5 NAND gates using 3 of the gates as inverters.
...
The logic was checked against the Simplified Schematic with thanks to http://www.neuroproductions.be/logic-lab/ for the simulator.
| Inputs Enable Select | Outputs | ||||||
|---|---|---|---|---|---|---|---|
| /CE | A | B | /Y3 | /Y2 | /Y1 | /Y0 | |
| 00 | 0 | 0 | 0 | 1 | 1 | 1 | 0 |
| 01 | 0 | 0 | 1 | 1 | 1 | 0 | 1 |
| 02 | 0 | 1 | 0 | 1 | 0 | 1 | 1 |
| 03 | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
| 1 | X | X | 1 | 1 | 1 | 1 | |
00
01
02
03
They both agree.
Circuit Diagram using
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4 decode chips.
To be drawn
Building the circuit on a breadboard externally
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