Tiny url http://tinyurl.com/jdp3qqr
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The Z88 only uses one half of this dual decode chip. This circuit may be made with
- 3 inverters
- 2 NAND gates
The inverters are slower than the NAND gates, so it was decided to use 5 NAND gates using 3 of the gates as inverters.
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| Part No | Chip | Manufacture | Speed nS | Package | Price | |||
|---|---|---|---|---|---|---|---|---|
| Min | Typ | Max | ||||||
| 1741279 | SN74LVC1G139DCTR | Ti | <2.5 | SM8 | $ 0.69 | |||
| SN74LVC1G139DCUT | Ti / Farnell | <2.5 | VSSOP | £0.404 | ||||
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| Inputs | Outputs | ||
|---|---|---|---|
| B /CE | A A19 | /Y1 /CE1 FLASH | /Y0 /CE0 RAM |
| 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 1 |
| 1 | X | 1 | 1 |
Circuit Diagram using
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2-to-4 Line Decoder
Updated 3/10/2016
Building the circuit on a breadboard externally
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The Games play without crashing.
Full 74139 Version Build
As the The decoder chip above works and that it . It replaces 1/4 of the 74139 , the most straightforward way of building for the Z88 design.
For the full version is to add 3 further chips to the design.
Logic Diagram
(to be changed)
Original
Cut Down Version using two inputs and two outputs
This ignores A1 GND line.
The Z88 only uses one half of this dual decode chip. This circuit may be made with
- 3 inverters
- 2 NAND gates
The inverters are slower than the NAND gates, so it was decided to use 5 NAND gates using 3 of the gates as inverters, adding 2 OR, dual logic gates to the outputs enables the /CE signal to the design.
Choosing the DUAL TWO-INPUT POSITIVE-OR GATE chip
Looking through the data sheets for a Texas Instruments VC1 chip found the following timings:-
| Part No | Chip | Manufacture | Speed nS | Package | Price | |||
|---|---|---|---|---|---|---|---|---|
| Min | Typ | Max | ||||||
| 1741279 | SN74LVC2G32QDCURQ1 | Ti | <2.5 | SM8 | $ 0.55 | |||
| SN74LVC1G139DCUT | Ti / Farnell | <2.5 | VSSOP | £0.404 | ||||
The 2-to-4 Line Decoder display fast times.
Here is the chip that has been chosen:-
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Full Data Sheet for SN74LVC2G32-Q1 DUAL TWO-INPUT POSITIVE-OR GATE & Timing
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This chip provides the logic for the /CE signal.
Circuit Description
There are 2 inputs A and B. The /CE signal enables the chip.
Logic Lab Test v Truth Table
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| Inputs Enable Select | Outputs | ||||||
|---|---|---|---|---|---|---|---|
| /CE | A | B | /Y3 | /Y2 | /Y1 | /Y0 | |
| 00 | 0 | 0 | 0 | 1 | 1 | 1 | 0 |
| 01 | 0 | 0 | 1 | 1 | 1 | 0 | 1 |
| 02 | 0 | 1 | 0 | 1 | 0 | 1 | 1 |
| 03 | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
| 1 | X | X | 1 | 1 | 1 | 1 | |
| /CE = 0 | /CE = 1 | |
|---|---|---|
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02 |
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03 |
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The eight combinations all agree.
http://www.neuroproductions.be/logic-lab/index.php?id=64582
http://www.neuroproductions.be/logic-lab/index.php?id=64583
The simulator file may be used and viewed at
http://www.neuroproductions.be/logic-lab/index.php?id=64758
Circuit Diagram using
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a 2-to-4 Line Decoder and 2 Dual OR Chips.
To be drawn
Building the circuit on a breadboard externally
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