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Internal EPROM (IC3). Read cycles for IC3 are preceded by writing all 0's to bits A21 - A19 of the appropriate address extension register within IC4. When the CPU enables the register, these bits are decoded to produce the active low chip enable signal for the EPROM, output as IPCE on IC4 pin 68. The active low output enable signal for IC3 is also decoded within IC4 from the /M1, /RD and /MREQ waveforms generated by the CPU during an instruction opcode fetch. In the appropriate combination, these signals generate ROE on IC4 pin 87, causing the EPROM to output data to IC4 on MDH - MDA from an address specified by MA15 - MA0. The latter comprises bits A13 - A0 output by the CPU as CA0 - CA13, and the bottom two bits of the gate array's address extension register. Data received from EPROM is Dated Gated within IC4 and presented to the CPU as CDH - CDA.
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