6. Memory Organisation

Internal memory for the Z88 is provided by a 32k byte pseudo-static RAM and a 128k byte EPROM. External RAM in the form of plug-in memory cards increases the available RAM by up to 3m bytes. Three slots each accept a 32k byte or 128k byte memory card with a lm byte memory card promised for early 1988.

Slot 3 has a dual function, accepting either a RAM or EPROM memory card. The latter (also available in three standard sizes) is used to archive files using the Z88's built-in EPROM programmer. (ROM memory cards are also available for test purposes and can be plugged into any of the slots).

Suffice it to say, it is necessary for the CPU to know the size and type of memory card in each of the slots. This information is determined when the CPU conducts selective read/write cycles to memory during power up and, in the case of slot 3, when the EPROM options are selected from the Filer menu.

Memory Addressing

The maximum addressable memory is 4m bytes, divided between lo byte of internal memory (1/2m byte each for RAM and EPROM) and 1m byte for each memory card slot.

Since the CPU's address bus limits direct memory access to 64k bytes, the width of the bus must be increased from 16 to 21 bits. This function is carried out using four address extension registers in the gate array located in the CPU I/O address space (see Figure 1.1).

The bottom six bits of each 8-bit register (Al9 - A14) provide a page address in the range 0 - 63, each page comprising 16k locations. This page reference, combined with the page offset address provided by the CPU on A13 -A0 allows access to any address in the range 0 - 1 Mbyte. Which lm byte segment of the 4m byte memory space is addressed in this way is determined by the top two bits in each extension register (A21 and A20). Internal memory occupies segment 0 and slots 1 to 3, segments 1, 2 and 3 respectively.

The extension register chosen to supply the page and segment address is determined by A15 and A14 output on the CPU address bus together with the page offset. This feature is useful since it allows the CPU to set up the registers once prior to accessing any contiguous 64k byte block of memory.

Access to either the EPROM or RAM resident within segment 0 is determined by address A19 within the appropriate extension register. A19 set high selects EPROM in the lower im byte, and when set low selects RAM in the upper half megabyte.

CPU access to the extension registers is using an I/O write instruction which also requires address bit A3 high.

Write Operations (Figure 1.6)

Memory read/write operations are decoded by the gate array using the /M1, /RD and /MREQ inputs from the CPU, and address bits A21 - A19 held in the address extension registers.

Internal EPROM (IC3). Read cycles for IC3 are preceded by writing all 0's to bits A21 - A19 of the appropriate address extension register within IC4. When the CPU enables the register, these bits are decoded to produce the active low chip enable signal for the EPROM, output as IPCE on IC4 pin 68. The active low output enable signal for IC3 is also decoded within IC4 from the /M1, /RD and /MREQ waveforms generated by the CPU during an instruction opcode fetch. In the appropriate combination, these signals generate ROE on IC4 pin 87, causing the EPROM to output data to IC4 on MDH - MDA from an address specified by MA15 - MA0. The latter comprises bits A13 - A0 output by the CPU as CA0 - CA13, and the bottom two bits of the gate array's address extension register. Data received from EPROM is Gated within IC4 and presented to the CPU as CDH - CDA.

Internal RAM (IC2). Read/write cycles for IC2 are preceded by writing 0's into bits A21 and A20 of the appropriate address extension register and a 1 into A19. When the CPU enables the register, these bits are decoded to produce the active low chip enable signal for the RAM, output as IRCE on IC4 pin 39. The active low output enable signal for IC2 is also decoded within IC4, as in the case of the EPROM, to produce POE on IC4 pin 87. Likewise, a memory read or memory write cycle is determined by IC4 from the state of /M1, /MREQ and /RD waveforms. IC4 pin 63 (/WR) is high for a read cycle and low for a write cycle.

NOTE: The printed circuit board is tracked for a 32-pin 128k byte RAM device. The circuit diagram is similarly configured. For the current 32k RAM device, pin 3 is read as pin 1, A16, A15 and POE are not used, and the CS signal (pin 28 on the 32k RAM) is VCC. In all other respects, the pinout of the two devices is identical.

External RAM. External RAM in slots 1 to 3 is accessed in a similar manner to the internal RAM except for the chip enable signals. Instead of IRCE, the gate array decodes the top two bits of the address extension register to produce individual slot enable signals SE1 to SE3 on IC4 pins 86, 93 and 91 respectively.

The top three bits of the address bus MA16 to MA19 are also available to each slot allowing up to lm byte of memory to be addressed.

External EPROM.

TBD - Awaiting imput from Cambridge Computer

Memory Refresh

The internal and external RAM is known as pseudo-static RAM, combining the high densitytlow cost benefits of a dynamic RAM with the static RAM's ability to retain data without the need for external refresh circuitry. Instead, refresh is carried out using the memory's on-chip refresh circuitry or, as is the normal case, when addressing the RAM to update the LCD display frame.

On-chip refresh, enabled only when the Z88 is in the coma state or the CPU is programming an EPROM, is achieved by simultaneously holding the /CE line to each RAM high (ie IRCE, and SE1 to SE3), and the /OE /RFSH line low (ie POE). At all other times, the RAM address range produced whilst updating the LCD display frame is sufficient to keep the RAM contents refreshed.

The occurrence of a refresh cycle conducted by the CPU at the end of each opcode fetch instruction is sensed by the gate array from a decode of the /M1, /MREQ and /RD signals and the corresponding refresh address placed on the address bus ignored.

Bus Protection

As a precaution, the Z88 is forced into the coma state whenever a memory card (or peripheral card) is plugged into or removed from one of the external slots. Insertion or removal of a card is detected when the edge connector sense line is pulled down to 0V. When this occurs, the gate array generates a non-maskable interrupt to the CPU causing the latter to initiate a controlled shutdown (see also para. 11.3.3).

Shaping the lands on the memory card edge connectors in the region of pins 15 to 17 ensures that pin 15 (SNS) is shorted to pins 16 and 17 (0V), except when the card is fully inserted in the slot. Other edge connector lands are cut such that the sense line is grounded first before the address and data line connections are made or broken during card insertion/removal.

A similar scheme is adopted for the peripheral expansion card, except that the edge connector lands on the Z88 pcb are cut. In this case, two sense lines are provided in positions 1A and 24A so that the above criteria are satisfied even when the peripheral card is skewed.