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The maximum addressable memory is 4m bytes, divided between lo byte of internal memory (Im 1/2m byte each for RAM and EPROM) and lm 1m byte for each memory card slot.
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CPU access to the extension registers is using an I/O write instruction which also requires address bit AS A3 high.
Write Operations (Figure 1.6)
Memory read/write operations are decoded by the gate array using the /MIM1, /RD and /REQ MREQ inputs from the CPU, and address bits A21 - A19 held in the address extension registers.
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Internal RAM (IC2). Read/write cycles for IC2 are preceded by writing 0's into bits A21 and A20 of the appropriate address extension register and a 1 into A19. When the CPU enables the register, these bits are decoded to produce the active low chip enable signal for the RAM, output as IRCE on IC4 pin 39. The active low output enable signal for IC2 is also decoded within IC4, as in the case of the EPROM, to produce POE on IC4 pin 87. Likewise, a memory read or memory write cycle is determined by IC4 from the state of /M1, /MREQ and /RD waveforms. IC4 pin 63 (/WR) is high for a read cycle and low for a write cycle.
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