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The bottom six bits of each 8-bit register (Al9 - A14) provide a page address in the range 0 - 63, each page comprising 16k locations. This page reference, combined with the page offset address provided by the CPU on A13 -A0 allows access to any address in the range O 0 - 1 Mbyte. Which lm byte segment of the 4m byte memory space is addressed in this way is determined by the top two bits in each extension register (A21 and A20). Internal memory occupies segment O 0 and slots 1 to 3, segments 1, 2 and 3 respectively.
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Access to either the EPROM or RAM resident within segment O 0 is determined by address A19 within the appropriate extension register. A19 set high selects EPROM in the lower im byte, and when set low selects RAM in the upper half megabyte.
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Internal EPROM (IC3). Read cycles for IC3 are preceded by writing all O0's to bits A21 - A19 of the appropriate address extension register within IC4. When the CPU enables the register, these bits are decoded to produce the active low chip enable signal for the EPROM, output as IPCE on IC4 pin 68. The active low output enable signal for IC3 is also decoded within IC4 from the /M1, /RD and /MREQ waveforms generated by the CPU during an instruction opcode fetch. In the appropriate combination, these signals generate ROE on IC4 pin 87, causing the EPROM to output data to IC4 on MDH - MDA from an address specified by MA15 - MA0. The latter comprises bits A13 - A0 output by the CPU as CA0 - CA13, and the bottom two bits of the gate array's address extension register. Data received from EPROM is Dated within IC4 and presented to the CPU as CDH - CDA.
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As a precaution, the Z88 is forced into the coma state whenever a memory card (or peripheral card) is plugged into or removed from one of the external slots. Insertion or removal of a card is detected when the edge connector sense line is pulled down to OV0V. When this occurs, the gate array generates a non-maskable interrupt to the CPU causing the latter to initiate a controlled shutdown (see also para. 11.3.3).
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