Introduction

The Z88 Flash/RAM card has been working for several years now. When OZ 4.6 was introduced, allowing applications to be run in RAM, some games failed to run.

This was thought to be due to an intermittent timing error from the decode chip CD74HCT139 which switches between the RAM and Flash chip but after the Z88 Hardware Investigation, it has been discovered to be a misunderstanding by both the hardware and software engineers on how to write faultlessly to the flash chip. This has only affected a few users, i.e. those who play games in RAM or who do repetitive writing to the flash card. The majority of users have not reported any problems.

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It has already been proved that if OZ 4.7 is run in a 256K EPROM card, the application runs faultlessly. This is because the code that the flash chip normally writes to the data bus is no longer written, as there is no flash chip. The OTP (One Time Programming) EPROM uses a similar footprint to the 512K Flash chip, so it was decided to try this combination and see if it improves the performance.

Two versions are being considered.

• 256K - for OZ 4.7 and
  768K of RAM
• 256K - for OZ 4.7 and
  768K of Flash

Although the best solution would be a software upgrade to OZ 4.7 allowing users to update their cards, it has been decided to see if by changing the hardware the same result may be achieved. See Writing to Flash Chips for a full explanation of what needs to be fixed. The object of this exercise is to run OZ 4.7 in the OTP EPROM in the top 256K area, leaving the rest of the address space 768K for either RAM, using the 1M RAM chip or Flash, using the 1M Flash chip. The only disadvantage is that users will no longer be able to update their OZ themselves, but a socket may be . A socket is fitted in the card, so that the OTP EPROM may be replaced.

The address decoding will be identical for both versions.

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The modified 512K/512K card has already been used with the modified extender card as described in the Z88 Hardware Investigation section, to test how the decoder chip may be used with different address maps. It was decided just to build a card using the knowledge gained from these previous tests.

Decoder

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Decoder Connections

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The decode chip used, is repeated twice in the same device. The first part does the 256K/768K chip select decodes the 256K EPROM. The unused decode is used to decode either the RAM or FLASH.

In all cases, the input pins of the unused part (Pins 13, 14 & 15), need to be isolated as they have been connected to GND.

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Details

The same decoding algorithm is used for both cards. The output is either connected to the CE of the RAM or FLASH chip.

256K OTP EPROM, 768K FLASH or RAM

Choosing the output

Using the signal that we wish to control as the Enable signal, choosing which out put is used is determined by A0 and A1. In this case they are both high, which means that Y3 is used.

• ROE to E (Pin 15)
• Vcc to A0 (Pin 14) for A19 high
• Vcc to A1 (Pin 13) for logic 1

The output was Y3 (Pin 9). It passed through the signal. The other 3 were high. Connecting MA19 and Vcc afterwards, the card worked perfectly.

This procedure was repeated for

• ROE to E (Pin 15)
• Vcc to A0 (Pin 14) for A19 high
• GND to A1 (Pin 13) for logic 0

The output was Y1 (Pin 11).

This was the final result as it would allow the Enable signal from the Z88 to be gated into the logic as well.

512K FLASH PROTECTED & 512 RAM

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Connection List 256K

Decoder Connections

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The decode chip used, is repeated twice in the same device. The first device decodes the 256K EPROM with SE1, A19 and A18. The unused decoder is used to select the remainder of the address space, when the card is selected but not the 256K EPROM. The output going to either the RAM or FLASH chip enable.

Selecting the decoder outputs

Connection List 1M

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Y0

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Y0

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Y1

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Y1

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Conclusion

Further testing will be done before reporting that a hardware solution has been found.

What has changed?

1. The chip select of the decoder remains unchanged.
   This selects the RAM Chip Enable when A19 is low and the FLASH Chip Enable when A19 is high.
2. The FLASH chip only uses its Chip Enable when it is read, like a ROM.
   The second independent part of the decoder does a similar function to the FLASH chip like the first, by only enabling its Output Enable signal with ROE, when A19 is high and Card Enable is low. This means that when the on board RAM is accessed, or the card is no longer enabled, the FLASH chip is no longer able to write to the data bus.
3. The extra circuitry does in effect the same thing as the chip enable, but gates the Output Enable signal. This prevents the flash chip from writing to the data bus when it is not selected.

POE & ROE

Splitting these two signals on the 512K/512K Flash/RAM card has made no difference. There are more cycles generated on the POE signal to refresh the RAM, but it was found that even Cambridge are using the ROE signal for their RAMs so it is proposed to leave ROE to Output Enable the FLASH and RAM as before.

Modifying Flash Cards

Some flash chips are better than others. What has been found is that it is possible to crash the Z88 consistently with one flash card and not with another one. It does not matter which size they are either. This is why not all users have experienced errors. It also depends what the user does. Just using Pipedream and saving files will not cause any errors.

New cards will be modified with these changes.

https://tinyurl.com/mkdlwv4

512K Flash Modifications

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Using the signal that we wish to control as the Enable signal, choosing which output is used is determined by A0 and A1. In this case they are both high, which means that Y3 is used.

• SE1 to E (Pin 1)
• MA19      (Pin 2) for A19 high
• MA18      (Pin 3) for A18 high

The output for the OTP EPROM CE is Y3 (Pin 7).

The same technique is repeated for

• SE1 to E (Pin 15)
• From OTP EPROM CE to A0 (Pin 14) for when it is high, the OTP is not selected
• GND to A1 (Pin 13) for logic 0

The output for the RAM or Flash is Y1 (Pin 11).

U3 Variants

U3 is currently wired up for a 512K Flash chip. There are 3 signals that use 2 different pins on the PLCC footprint.

These are displayed in the following table.

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If links are to be used on a future designed board the following layout maybe considered

The 256K PROM is being used 
Vpp needs to be connected to pin 1
PGM is already connected to pin 31

PCB Modifications

Connection Chart

256K OTP EPROM 768 RAM Modifications follows

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256K OTP EPROM 768 FLASH Modifications follow

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Conclusion

Further testing will be done before reporting that a hardware solution has been found.