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Since the CPU's address bus limits direct memory access to 64k bytes, the width of the bus must be increased from 16 to 21 bits. This function is carried out using four address extension registers in the gate array located in the CPU I/O address space (see Figure 1.1).
The bottom six bits of each 8-bit register (Al9 - A14) provide a page address in the range 0 - 63, each page comprising 16k locations. This page reference, combined with the page offset address provided by the CPU on A13 -A0 allows access to any address in the range 0 - 1 Mbyte. Which lm byte segment of the 4m byte memory space is addressed in this way is determined by the top two bits in each extension register (A21 and A20). Internal memory occupies segment 0 and slots 1 to 3, segments 1, 2 and 3 respectively.
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