Tiny url http://tinyurl.com/jdp3qqr

Introduction

Some games that run in RAM, particularly when in combination with OZ v4.6 and later - running in slot 1, fails to run on the 512K/512K Flash/RAM Card. This has been due to a timing error which was introduced by the decode chip CD74HCT139 which switches between the RAM and Flash chip.

Although this is one of the fastest decode chips, it has been proved to be too slow for our purposes.

Object

The object of this exercise is to see if by redefining the design on a small PCB, with the same footprint of the existing decode chip, a faster decode could be achieved by

1. Using high speed NAND gates, to see if then if that was successful
2. Then try using a decode chip from the same family.
3. Using the knowledge gained, add the circuit on the card to add the components to make a high speed 74139.

The Z88 only uses one half of the dual functionality of the full chip.

Adding 3 more of these decode chips allow full functionality using four 3mm wide high speed chips.

See http://www.neuroproductions.be/logic-lab/index.php?id=63191 for the ongoing logic in checking that the full chip will work. 

NAND Gate Build

Choosing a Fast NAND gate

Looking through the datasheets for NAND gates found the following timings:-

The Single 2-input Positive NAND gates display the fastest times.

Here is the chip that has been chosen:-

Full Data Sheet for SN74LVC1G00 Single 2-Input Positive-NAND Gate & Timing

Circuit Description

There are 2 inputs,

• A19 - Selects either the top half of the 1M memory space for the flash chip or the bottom half for the RAM.
• /CE - Selects the 1M card.

Truth Table of half a 74139 using two outputs

Logic Diagram

Original

Cut Down Version using two inputs and two outputs

This ignores A1 GND line.

The Z88 only uses one half of this dual decode chip. This circuit may be made with

• 3 inverters
• 2 NAND gates

The inverters are slower than the NAND gates, so it was decided to use 5 NAND gates using 3 of the gates as inverters.

Logic Lab Test v Truth Table

The logic was checked with thanks to http://www.neuroproductions.be/logic-lab/ for the simulator.

They both agree.

Circuit Diagram

Circuit updated 15:04 6/9/16

Building a prototype board internally

A prototype board was built inside the Flash card..

07/09/16

It was very difficult to solder onto the legs of the inverted small chips. As a result, this prototype failed to work.

Building the circuit on a breadboard externally

Components required

10 sot to IC adaptors were obtained in addition to the 5 NAND gates.
The circuit could now be bread-boarded and tested outside the Z88 card case.

The four signal and power lines can be seen connecting the card to the breadboard.

Plan view showing all the connections.

Oscilloscope Readings

This produced the signals required.

This trace shows the Flash chip being selected (/CE1) in 3nS.

The RAM (/CE) would be the same timings.

Printed Circuit Board

http://tinyurl.com/h8dxsct

A PCB has been laid out (just in case Tony's prototype works), but this was never produced due to ongoing development.

Main points

• A letterbox slot has been made in the centre of the HD1, HD2, (which are connected both sides,) so that either direct soldering or wire links may be used to connect the signals from the 512K/512K card to the PCB.
• The pads of the footprint of the SOT-23-5 have been made longer, to enable easier soldering of the small parts.
• The bottom Left Hand corner of the PCB matches the shape of the 512K/512K Card for easy alignment.
• C2 on the 512K/512K, needs to be removed and put onto the PCB, in the same space. This is to make the PCB a bit larger for stability.

The 7 layers

Here are the layers printed on A4 sheets. The board is small, zooming in is generally helpful.

(updated 19:16 07/09/2016)

Results

The latest software was tried again in a standard 512K/512K Flash/RAM Card and Vic could not make the games software go wrong. The prototype board was packed and sent to Mr T who had a failing Z88 and 512K/512K Flash/RAM Card. He confirmed that it was the decoder chip that was causing the fault and suggested that another decoder could be found.

DECODER Chip Build

http://tinyurl.com/j6zkfaj

Using 5 NAND Gates to prove that there is a hardware problem was very useful, but for a production run using a single chip to replace these is the next step.

Choosing a Decoder chip

Looking through the data sheets for a Texas Instruments VC1 chip found the following timings:-

The 2-to-4 Line Decoder display fast times.

Here is the chip that has been chosen:-

Full Data Sheet for SN74LVC1G139 2-to-4 Line Decoder & Timing

This chip on its own provides the logic for the Z88 application.

Circuit Description

There are 2 inputs,

• A19 - Selects either the top half of the 1M memory space for the flash chip or the bottom half for the RAM using the A input.
• /CE - Selects this chip.

Truth Table of Decode Chip

Circuit Diagram using 2-to-4 Line Decoder

 
Updated 3/10/2016

Building the circuit on a breadboard externally

Components required

2 MSOP-8 AND 1 VSOP to IC adaptors were obtained in addition to the 5 2-to-4 Line Decoder chips.
This circuit could now be bread-boarded and tested outside the Z88 card case.

The four signal and power lines can be seen connecting the card to the breadboard.

The Games play without crashing.

Full 74139 Version Build

Tiny url http://tinyurl.com/zf9haly

The decoder chip above works. It replaces 1/4 of the 74139 for the Z88 design.

For the full version, adding 2 OR, dual logic gates to the outputs enables the /CE signal to the design.

Choosing the DUAL TWO-INPUT POSITIVE-OR GATE chip

Looking through the data sheets for a Texas Instruments VC1 chip found the following timings:-

The 2-to-4 Line Decoder display fast times.

Here is the chip that has been chosen:-

Full Data Sheet for SN74LVC2G32-Q1 DUAL TWO-INPUT POSITIVE-OR GATE & Timing

This chip provides the logic for the /CE signal.

Circuit Description

There are 2 inputs A and B. The /CE signal enables the chip.

Logic Lab Test v Truth Table

The logic was checked against the Simplified Schematic with thanks to http://www.neuroproductions.be/logic-lab/ for the simulator.

The eight combinations all agree.

http://www.neuroproductions.be/logic-lab/index.php?id=64582

http://www.neuroproductions.be/logic-lab/index.php?id=64583

The simulator file may be used and viewed at

http://www.neuroproductions.be/logic-lab/index.php?id=64758

Circuit Diagram using a 2-to-4 Line Decoder and 2 Dual OR Chips.

2-to-4 Line Decoder

Updated 17/11/2016

All the components required cannot be fitted on a single card. The design has been split onto two cards. The first PCB is just for the Z88.

2-to-4 Line Decoder and 2 Dual OR Chips

If a full 74139 chip is required another PCB with the extra components can be either

• piggy backed (using the DIL connections) to this card if the 16 Pin SOIC footprint is required or
• plugged into a 16 pin DIL socket.

Building the circuit on a breadboard externally

Components required

2 MSOP-8 IC adaptors were obtained in addition to the DUAL TWO-INPUT POSITIVE-OR GATE chips. 
This circuit could now be bread-boarded and tested.

This photo needs to be replaced

The four signal and power lines can be seen connecting the card to the breadboard.

This picture needs to be replaced.

The Games play without crashing.

Oscilloscope Readings

(This picture needs replacing)

This produced the signals required.

This trace shows the Flash chip being selected (/CE1) in 3nS.

The RAM (/CE) would be the same timings.

Printed Circuit Board

2-to-4 Line Decoder

Main points

• Small holes are drilled in the centre of the pads of H1,so that wire links may be used to connect the signals from the 512K/512K card to the PCB.
• The pads of the footprint of the SOT-23-5 have been made longer, to enable easier soldering of the small parts.
• The bottom Left Hand corner of the PCB matches the shape of the 512K/512K Card for easy alignment.

Provisional Layout

The 7 layers

Here are the layers printed on A4 sheets. The board is small, zooming in is generally helpful.

To be done