Tiny url http://tinyurl.com/jdp3qqr
Introduction
Some games that run in RAM, particularly when in combination with OZ v4.6 and later - running in slot 1, fails to run on the 512K/512K Flash/RAM Card. This may be due to a timing error which is introduced by the decode chip CD74HCT139. Although this is one of the fastest decode chips, it is too slow for our purposes.
The Z88 only uses one half of this dual decode chip. This circuit may be made with
- 3 inverters
- 2 NAND gates
The inverters are slower than the NAND gates, so it was decided to use 5 NAND gates using 3 of the gates as inverters.
The object of this exercise is to see if by redefining the design, a faster decode is achieved by using the NAND gates that are required.
Choosing a fast NAND gate
Looking through the datasheets for NAND gates found the following timings:-
| Part No | Chip | Manufacture | Speed | Package | Price | ||||
|---|---|---|---|---|---|---|---|---|---|
| Min | Typ | Max | |||||||
| 1085297 | 74HCT00D | NXP | 10nS | SOIC | 0.221 | ||||
| 381755 | 74HCT00N | NXP | 10nS | DIP | 0.667 | ||||
| 9590889 | 74HC00 | Ti | 8nS | DIP | 0.31 | ||||
| 1105915 | SN74AHCIG00 | Ti | 5,2 | 8 mA | SOT-23-5 | 1.78 | |||
| 1287697 | SN74LVCIG007 SN74LVC1G00DBVR | Ti | 4.0 | 32mA | SOT-23-5 | 1.98 | |||
| SN74LVC1G00-EP | Ti | 1.0 | 4.0 | ||||||
| SN74LVC1G00DBVR | Ti | 1.0 | 4.0 | SOT-23-5 | |||||
The Single 2-input Positive NAND gates display the fastest times.
Here is the chip that has been chosen:-
Circuit Description
There are 2 inputs,
- A19 - Selects either the top half of the 1M memory space for the flash chip or the bottom half for the RAM.
- /CE - Selects the 1M card.
Truth Table of the 74139
| Inputs Enable Select | Outputs | |||
|---|---|---|---|---|
| /E /CE | A1 | A0 A19 | /Y1 /CE1 FLASH | /Y0 /CE0 RAM |
| 0 | 0 | 0 | 1 | 0 |
| 0 | 0 | 1 | 0 | 1 |
| 1 | X | X | 1 | 1 |
Logic Diagram
Original
Cut Down Version using two inputs and two outputs
This ignores A1 GND line.
Logic Lab Test v Truth Table
The logic was checked with thanks to http://www.neuroproductions.be/logic-lab/ for the simulator.
| Inputs Enable Select | Outputs | |||
|---|---|---|---|---|
| /E /CE | A0 A19 | /Y1 /CE1 FLASH | /Y0 /CE0 RAM | |
| 00 | 0 | 0 | 1 | 0 |
| 01 | 0 | 1 | 0 | 1 |
| 02 | 1 | 0 | 1 | 1 |
| 03 | 1 | 1 | 1 | 1 |
00
01
02
03
They both agree.
Circuit Diagram
Circuit updated 15:04 6/9/16
Can a Full 74139 chip be built?
The Z88 only uses one half of the dual functionality of the full chip.
Using just NAND gates requires too many of them. See http://www.neuroproductions.be/logic-lab/index.php?id=63191 for the unfinished work in getting a full chip to work.
Prototype Board
A prototype board is being built, here are the power connections
.
Printed Circuit Board
A PCB has been laid out (just in case Tony's prototype works).
Main points
- A letterbox slot has been made in the centre of the HD1, HD2, (which are connected both sides,) so that either direct soldering or wire links may be used to connect the signals from the 512K/512K card to the PCB.
- The pads of the footprint of the SOT-23-5 have been made longer, to enable easier soldering of the small parts.
- The bottom Left Hand corner of the PCB matches the shape of the 512K/512K Card for easy alignment.
- C2 on the 512K/512K, needs to be removed and put onto the PCB, in the same space. This is to make the PCB a bit larger for stability.
The 7 layers
Here are the layers printed on A4 sheets. The board is small, zooming in is generally helpful.
(updated 14:54 6/9/16)