Tiny url http://tinyurl.com/jdp3qqr
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Introduction
Some games that run in RAM, particularly when in combination with OZ v4.6 and later - running in slot 1, fails to run on the 512K/512K Flash/RAM Card. This has been due to a timing error which was introduced by The Z88 Flash/RAM card has been working for several years now. When OZ 4.6 was introduced, allowing applications to be run in RAM, some games failed to run.
This was found to be due to an intermittent timing error from the decode chip CD74HCT139 which switches between the RAM and Flash chip.
Although this is one of the fastest decode chips, taking 10nS, it has been proved to be too slow for our purposesthe software speed improvements pushed it outside these limits.
This documents highlights the steps taken to rectify this. The detail of the steps taken are now in subsections allowing the reader to go into detail if required.
Object
The object of this exercise is to see if by redefining the design on a small PCB, with the same footprint of the existing decode chip, a faster decode could be achieved by
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See http://www.neuroproductions.be/logic-lab/index.php?id=63191 for the ongoing logic in checking that the full chip will work.
NAND Gate Build
Choosing a Fast NAND gate
Looking through the datasheets for NAND gates found the following timings:-
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SOT-23-5
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The Single 2-input Positive NAND gates display the fastest times.
Here is the chip that has been chosen:-
Full Data Sheet for SN74LVC1G00 Single 2-Input Positive-NAND Gate & Timing
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Circuit Description
There are 2 inputs,
- A19 - Selects either the top half of the 1M memory space for the flash chip or the bottom half for the RAM.
- /CE - Selects the 1M card.
Truth Table of half a 74139 using two outputs
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A1
GND
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Logic Diagram
Original
Cut Down Version using two inputs and two outputs
This ignores A1 GND line.
The Z88 only uses one half of this dual decode chip. This circuit may be made with
- 3 inverters
- 2 NAND gates
The inverters are slower than the NAND gates, so it was decided to use 5 NAND gates using 3 of the gates as inverters.
Logic Lab Test v Truth Table
The logic was checked with thanks to http://www.neuroproductions.be/logic-lab/ for the simulator.
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They both agree.
Circuit Diagram
Circuit updated 15:04 6/9/16
Building a prototype board internally
A prototype board was built inside the Flash card..
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It was very difficult to solder onto the legs of the inverted small chips. As a result, this prototype failed to work.
Building the circuit on a breadboard externally
Components required
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10 sot to IC adaptors were obtained in addition to the 5 NAND gates .
The circuit could now be bread-boarded and tested outside the Z88 card case.
The four signal and power lines can be seen connecting the card to the breadboard.
Plan view showing all the connections.
Oscilloscope Readings
This produced the signals required.
This trace shows the Flash chip being selected (/CE1) in 3nS.
The RAM (/CE) would be the same timings.
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| title | Signals not the same abbreviations as the circuit |
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The names of the signals on the scope are not all the same as shown in the circuit.
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Printed Circuit Board
A PCB has been laid out (just in case Tony's prototype works), but this was never produced due to ongoing development.
Main points
- A letterbox slot has been made in the centre of the HD1, HD2, (which are connected both sides,) so that either direct soldering or wire links may be used to connect the signals from the 512K/512K card to the PCB.
- The pads of the footprint of the SOT-23-5 have been made longer, to enable easier soldering of the small parts.
- The bottom Left Hand corner of the PCB matches the shape of the 512K/512K Card for easy alignment.
- C2 on the 512K/512K, needs to be removed and put onto the PCB, in the same space. This is to make the PCB a bit larger for stability.
The 7 layers
Here are the layers printed on A4 sheets. The board is small, zooming in is generally helpful.
(updated 19:16 07/09/2016)
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were used to test whether a faster time could be achieved with the Z88.
Results
The latest software was tried again in a standard 512K/512K Flash/RAM Card and Vic could not make the games software go wrong. The prototype board was packed and sent to Mr T who had a failing Z88 and 512K/512K Flash/RAM Card. He confirmed that it was the decoder chip that was causing the fault and suggested that another decoder could be found.
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Using 5 NAND Gates to prove that there is a hardware problem was very useful, but for a production run using a single chip to replace these is the next step.
Choosing a Decoder chip
Looking through the data sheets for a Texas Instruments VC1 chip found the following timings:-
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SN74LVC1G139DCTR
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The 2-to-4 Line Decoder display fast times.
Here is the chip that has been chosen:-
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-to-4 Line Decoder
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This chip on its own provides the logic for the Z88 application.
Circuit Description
There are 2 inputs,
- A19 - Selects either the top half of the 1M memory space for the flash chip or the bottom half for the RAM using the A input.
- /CE - Selects this chip.
Truth Table of Decode Chip
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Circuit Diagram using 2-to-4 Line Decoder
Updated 3/10/2016
Building the circuit on a breadboard externally
Components required
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2 MSOP-8 AND 1 VSOP to IC adaptors were obtained in addition to the 5 2-to-4 Line Decoder chipsto replace them is the next step.
This circuit could now be bread-boarded and tested outside the Z88 card case.
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The Games play without crashing.
Printed Circuit Board
2-to-4 Line Decoder
Provisional Layout
Full 74139 Version Build
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| Part No | Chip | Manufacture | Speed nS | Package | Price | |||
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| Min | Typ | Max | ||||||
| 1741279 | SN74LVC2G32QDCURQ1 | Ti | <2.5 | SM8 | $ 0.55 | |||
| SN74LVC1G139DCUT | Ti / Farnell | <2.5 | VSSOP | £0.404 | ||||
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This chip provides the logic for the /CE signal.
Circuit Description
There are 2 inputs A and B. The /CE signal enables the chip.
Logic Lab Test v Truth Table
The logic was checked against the Simplified Schematic with thanks to http://www.neuroproductions.be/logic-lab/ for the simulator.
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Circuit Diagram using a 2-to-4 Line Decoder and 2 Dual OR Chips.
2-to-4 Line Decoder
Updated 17/11/2016
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- piggy backed (using the DIL connections) to this card if the 16 Pin SOIC footprint is required or
- plugged into a 16 pin DIL socket.
Building the circuit on a breadboard externally
Components required
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2 MSOP-8 IC adaptors were obtained in addition to the DUAL TWO-INPUT POSITIVE-OR GATE chips.
This circuit could now be bread-boarded and tested.
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The Games play without crashing.
Oscilloscope Readings
(This picture needs replacing)
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The names of the signals on the scope are not all the same as shown in the circuit.
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Printed Circuit Board
2-to-4 Line Decoder
Main points
- Small holes are drilled in the centre of the pads of H1,so that wire links may be used to connect the signals from the 512K/512K card to the PCB.
- The pads of the footprint of the SOT-23-5 have been made longer, to enable easier soldering of the small parts.
- The bottom Left Hand corner of the PCB matches the shape of the 512K/512K Card for easy alignment.
Provisional Layout
The 7 layers
Here are the layers printed on A4 sheets. The board is small, zooming in is generally helpful.
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