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The Z88 Flash/RAM card has been working for several years now. When OZ 4.6 was introduced, allowing applications to be run in RAM, some games failed to run.
Standard Version | Modified Turbo Monitoring Version |
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This was thought to be due to an intermittent timing error from the decode chip CD74HCT139 which switches between the RAM and Flash chip but after the Z88 Hardware Investigation, it has been discovered to be a misunderstanding by both the hardware and software engineers on how to write faultlessly to the flash chip.
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Although the best solution would be a software upgrade to OZ 4.7 allowing users to update their cards, it has been decided to see if by changing the hardware the same result may be achieved. See Writing to Flash Chips for a full explanation of what needs to be fixed. NOTE: This needs to be updated with the results found here.
The object of this exercise is to see if by redefining the address map and by hardware prevent this prevents the flash chip from writing to the data bus when it is running OZ 4.7.
It has already been proved that if OZ 4.7 is run in a 256K EPROM card, the application runs faultlessly. This is because the code that the flash chip normally writes to the Flash chip is ignored by the EPROM. There are several ways of achieving the same effect by changing the address mapping in the 1M space available on the card.data bus is no longer written, as there is no flash chip.
Although using an EPROM was considered, the Protect Flash version was tried first. This worked allowing the EPROM versions to be discarded.
Method
The modified 512K/512K card was used with the modified extender card as described in the Z88 Hardware Investigation section.
Decoder Tests
The decode circuits (one chip 74139) were built on a breadboard externally using DIL instead of using the SMD used on the card for easier testing, with flying wires to connect signals to the card and oscilloscope.
16 pin DIL | 16 pin SO 16 |
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EPROM | FLASH | RAM | |||||||
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OZ 4.7 | FILES | PROTECTED | FILES | CE | A19 | A18 | ROE | ||
Replace Flash with EPROM 1 | 256K | 768K | X | X | X | ||||
Replace Flash with EPROM 2 | 256K | 256K | 512K | X | X | ||||
Protect Flash | 256K | 256K | 512K | X | X | X | X |
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The decode chip used, is repeated twice in the same device. The first part does the 512K/512K Decode chip select decode between the RAM and FLASH (as before) whilst the . The unused part decode is used for the changesROE and ROE_S the additional circuitry.
In all cases, the input pins of the unused part (Pins 13, 14 & 15), need to be isolated as they have been connected to GND.
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Protect Flash
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256K EPROM 768 FLASH PROTECTED, 256K FLASH & 512 RAM
CE | A19 | A18 | ||
---|---|---|---|---|
256K EPROM | 0 | 1 | 1 | |
768K RAM | 0ROES | |||
256K FLASH PROTECTED | X | 1 | 1 | 1 |
256K FLASH | 1 | 1 | 0 | ROE |
512K RAM | 0 | 0 |
Initially it was decided to protect the top 256K of the Flash chip, where OZ 4.7 is, but it was found that if that area was protected, the Z88 would only see 256K of Flash with no File Area. Using a trial and error technique, it was found by adopting the following connection list, the card worked perfectly.
512K FLASH PROTECTED & 512 RAM
CE | A19 | LOGIC 1 | ROES | |
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256K FLASH PROTECTED | X | 1 | 1 | 1 |
256K FLASH | 1 | 1 | 0 | ROE |
512K RAM | 0 | 0 |
Connection List
I/O | E | A0 | A1 | PIN No | I/O | PIN No | ||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CEFROM Z88 SE1 | I | E | 1 | 0 | 1 | 0 | 0 | 0CEFLS | FROM Z88 ROE | I | E | 15 | 0 | 1 | 0 | 0 | 0 | |||||||
FROM Z88 MA19 | I | A0 | 2 | 0 | x | 1 | 0 | 1A19 | FROM Z88 MA19 | I | A0 | 14 | 0 | x | 1 | 0 | 1 | |||||||
LOGIC 0 - 0v | I | A1 | 3 | 0 | x | 0 | 1 | 1A18 | LOGIC 1 - Vcc | I | A1 | 13 | 0 | x | 0 | 1 | 1CERA | |||||||
TO RAM CE | O | 0 | 0 | 0 | Y0 | 4 | 1 | 1 | 1 | 1 | 0 | CERA | O | Y0 | 12 | 1 | 1 | 1 | 1 | 0 | CE TO RAM | CEFLS | ||
TO FLASH CE | O | 0 | 0 | 1 | Y1 | 5 | 1 | 1 | 1 | 0 | 1CEFL | O | Y1 | 11 | 1 | 1 | 1 | 0 | 1 | CE TO EPROM |
Replace Flash with EPROM 2
512K EPROM 512 RAM
NO CHANGE TO DECODE CHIP
PIN No | CE | E | 1O | 0 | 1 | 0 | 0Y2 | 06 | A19O | A0Y2 | 210 | 01 | x | 1 | 0 | 1 | 0v | A1 | 3 | 0 | x1 | ||||||||
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O | 0 | 1 | 1 | CERAY3 | Y0 | 4 | 1 | 1 | 17 | TO FLASH ROE_S | O | Y3 | 9 | 1 | 0 | CEFL | Y1 | 51 | 1 | 1 | 0|||||||||
1 |
Protect Flash
256K FLASH PROTECTED, 256K FLASH & 512 RAM
CE | A19 | A18 | ROES | 256K FLASH PROTECTEDX | X | 1 | 1 | 1 | 256K FLASH | 1 | 1 | 0 | ROE | 512K RAM | 0 | 0 |
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As all the inputs on the 2nd decoder have been tied to LOGIC 0 - GND, pin 13 was changed to GND, which moved the output (ROE_S) from pin 9 (Y3) to pin 11 (Y1).
Connection List
I/O | PIN No | I/O | PIN No | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FROM Z88 CE | I | E | 1 | 0 | 1 | 0 | 0 | 0 | FROM Z88 ROE | I | E | 15 | 0 | 1 | 0 | 0 | 0 | |
FROM Z88 A19 | I | A0 | 2 | 0 | x | 1 | 0 | 1 | FROM Z88 A19 | I | A0 | 14 | 0 | x | 1 | 0 | 1 | |
LOGIC 0 - 0v | I | A1 | 3 | 0 | x | 0 | 1 | 1 |
LOGIC 0 - GND | I | A1 | 13 | 0 | x | 0 | 1 | 1 |
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TO RAM CE | O | Y0 | 4 | 1 | 1 | 1 | 1 | 0 | O | Y0 | 12 | 1 | 1 | 1 | 1 | 0 |
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TO FLASH CE | O | Y1 | 5 | 1 | 1 | 1 | 0 | 1 | TO FLASH ROE_S | O | Y1 | 11 | 1 | 1 | 1 | 0 | 1 | |
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O | Y2 | 6 | O | Y2 | 10 | 1 | 1 | 0 | 1 | 1 | ||||||||
O | Y3 | 7 |
Decoder Tests
The decode circuits were built on a breadboard externally using DIL instead of using the SMD used on the card for easier testing.
O | Y3 | 9 | 1 | 0 | 1 | 1 | 1 |
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Conclusion
It has been a long journey to get to this point, but we are pleased to report that a hardware solution has been found.
What has changed?
- The chip select of the decoder remains unchanged.
This selects the RAM Chip Enable when A19 is low and the FLASH Chip Enable when A19 is high. - The FLASH chip only uses its Chip Enable when it is read, like a ROM.
The second independent part of the decoder does a similar function to the FLASH chip like the first, by only enabling its Output Enable signal with ROE, when A19 is high. This means that when the RAM is accessed, the FLASH chip is no longer able to write to the data bus.
POE & ROE
Splitting these two signals on the 512K/512K Flash/RAM card has made no difference. There are more cycles generated on the POE signal to refresh the RAM, but it was found that even Cambridge are using the ROE signal for their RAMs so it is proposed to leave ROE to Output Enable the FLASH and RAM as before.
Modifying Flash Cards
Some flash chips are better than others. What has been found is that it is possible to crash the Z88 consistently with one flash card and not with another one. It does not matter which size they are either. This is why not all users have experienced errors. It also depends what the user does. Just using Pipedream and saving files will not cause any errors.
New cards will be modified with these changes.