Introduction

The Z88 Flash/RAM card has been working for several years now. When OZ 4.6 was introduced, allowing applications to be run in RAM, some games failed to run.

This was thought to be due to an intermittent timing error from the decode chip CD74HCT139 which switches between the RAM and Flash chip but after the Z88 Hardware Investigation, it has been discovered to be a misunderstanding by both the hardware and software engineers on how to write faultlessly to the flash chip. This has only affected a few users, i.e. those who play games in RAM or who do repetitive writing to the flash card. The majority of users have not reported any problems. 

Object

Although the best solution would be a software upgrade to OZ 4.7 allowing users to update their cards, it has been decided to see if by changing the hardware the same result may be achieved. See Writing to Flash Chips for a full explanation of what needs to be fixed. NOTE: This needs to be updated with the results found here.

The object of this exercise is to see if redefining the address map by hardware this prevents the flash chip from writing to the data bus when it is running OZ 4.7.

It has already been proved that if OZ 4.7 is run in a 256K EPROM card, the application runs faultlessly. This is because the code that the flash chip normally writes to the data bus is no longer written, as there is no flash chip.

Although using an EPROM was considered, the Protect Flash version was tried first. This worked allowing the EPROM versions to be discarded.

Method

The modified 512K/512K card was used with the modified extender card as described in the Z88 Hardware Investigation section.

Decoder Tests

The decode circuits (one chip 74139) were built on a breadboard externally using DIL instead of using the SMD used on the card for easier testing, with flying wires to connect signals to the card and oscilloscope.

Decoder Connections

The decode chip used, is repeated twice in the same device. The first part does the 512K/512K chip select decode between the RAM and FLASH (as before). The unused decode is used for the ROE and ROE_S the additional circuitry.

In all cases, the input pins of the unused part (Pins 13, 14 & 15), need to be isolated as they have been connected to GND.

Protect Flash

256K FLASH PROTECTED, 256K FLASH & 512 RAM

Initially it was decided to protect the top 256K of the Flash chip, where OZ 4.7 is, but it was found that if that area was protected, the Z88 would only see 256K of Flash with no File Area.

Choosing the output

Using the signal that we wish to control as the Enable signal, choosing which out put is used is determined by A0 and A1. In this case they are both high, which means that Y3 is used.

• ROE to E (Pin 15)
• Vcc to A0 (Pin 14) for A19 high
• Vcc to A1 (Pin 13) for logic 1

The output was Y3 (Pin 9). It passed through the signal. The other 3 were high. Connecting MA19 and Vcc afterwards, the card worked perfectly.

This procedure was repeated for

• ROE to E (Pin 15)
• Vcc to A0 (Pin 14) for A19 high
• GND to A1 (Pin 13) for logic 0

The output was Y1 (Pin 11).

This was the final result as it would allow the Enable signal from the Z88 to be gated into the logic as well.

512K FLASH PROTECTED & 512 RAM

Connection List 512K

Connection List 1M

Conclusion

Further testing will be done before reporting that a hardware solution has been found.

What has changed?

1. The chip select of the decoder remains unchanged.
   This selects the RAM Chip Enable when A19 is low and the FLASH Chip Enable when A19 is high.
2. The FLASH chip only uses its Chip Enable when it is read, like a ROM.
   The second independent part of the decoder does a similar function to the FLASH chip like the first, by only enabling its Output Enable signal with ROE, when A19 is high and Card Enable is low. This means that when the on board RAM is accessed, or the card is no longer enabled, the FLASH chip is no longer able to write to the data bus.
3. The extra circuitry does in effect the same thing as the chip enable, but gates the Output Enable signal. This prevents the flash chip from writing to the data bus when it is not selected.

POE & ROE

Splitting these two signals on the 512K/512K Flash/RAM card has made no difference. There are more cycles generated on the POE signal to refresh the RAM, but it was found that even Cambridge are using the ROE signal for their RAMs so it is proposed to leave ROE to Output Enable the FLASH and RAM as before.

Modifying Flash Cards

Some flash chips are better than others. What has been found is that it is possible to crash the Z88 consistently with one flash card and not with another one. It does not matter which size they are either. This is why not all users have experienced errors. It also depends what the user does. Just using Pipedream and saving files will not cause any errors.

New cards will be modified with these changes.

https://tinyurl.com/mkdlwv4

512K Flash Modifications

1M Flash Modifications