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The decode circuits (one chip 74139) were built on a breadboard externally using DIL instead of using the SMD used on the card for easier testing, with flying wires to connect signals to the card and oscilloscope.
| 16 pin DIL | 16 pin SO 16 |
|---|---|
|
|
| EPROM | FLASH | RAM | |||||||
|---|---|---|---|---|---|---|---|---|---|
| OZ 4.7 | FILES | PROTECTED | FILES | CE | A19 | A18 | ROE | ||
| Replace Flash with EPROM 1 | 256K | 768K | X | X | X | ||||
| Replace Flash with EPROM 2 | 256K | 256K | 512K | X | X | ||||
| Protect Flash | 256K | 256K | 512K | X | X | X | X | ||
...
512K FLASH PROTECTED & 512 RAM
| CE | A19 | LOGIC 1 | ROES | |
|---|---|---|---|---|
| 256K FLASH PROTECTED | X | 1 | 1 | 1 |
| 256K FLASH | 1 | 1 | 0 | ROE |
| 512K RAM | 0 | 0 |
Connection List
| I/O | E | A0 | A1 | PIN No | I/O | PIN No | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| FROM Z88 SE1 | I | E | 1 | 0 | 1 | 0 | 0 | 0 | FROM Z88 ROE | I | E | 15 | 0 | 1 | 0 | 0 | 0 | ||||
| FROM Z88 MA19 | I | A0 | 2 | 0 | x | 1 | 0 | 1 | FROM Z88 MA19 | I | A0 | 14 | 0 | x | 1 | 0 | 1 | ||||
| LOGIC 0 - 0v | I | A1 | 3 | 0 | x | 0 | 1 | 1 | LOGIC 1 - Vcc | I | A1 | 13 | 0 | x | 0 | 1 | 1 | ||||
| TO RAM CE | O | 0 | 0 | 0 | Y0 | 4 | 1 | 1 | 1 | 1 | 0 | O | Y0 | 12 | 1 | 1 | 1 | 1 | 0 | ||
| TO FLASH CE | O | 0 | 0 | 1 | Y1 | 5 | 1 | 1 | 1 | 0 | 1 | O | Y1 | 11 | 1 | 1 | 1 | 0 | 1 | ||
| O | 0 | 1 | 0 | Y2 | 6 | O | Y2 | 10 | 1 | 1 | 0 | 1 | 1 | ||||||||
| O | 0 | 1 | 1 | Y3 | 7 | TO FLASH ROE_S | O | Y3 | 9 | 1 | 0 | 1 | 1 | 1 | |||||||
| 1 | X | X | 1 | 1 | 1 | 1 |
As all the inputs on the 2nd decoder have been tied to LOGIC 0 - GND, pin 13 was changed to GND, which moved the output (ROE_S) from pin 9 (Y3) to pin 11 (Y1).
Connection List
| I/O | PIN No | I/O | PIN No | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| FROM Z88 CE | I | E | 1 | 0 | 1 | 0 | 0 | 0 | FROM Z88 ROE | I | E | 15 | 0 | 1 | 0 | 0 | 0 | |
| FROM Z88 A19 | I | A0 | 2 | 0 | x | 1 | 0 | 1 | FROM Z88 A19 | I | A0 | 14 | 0 | x | 1 | 0 | 1 | |
| LOGIC 0 - 0v | I | A1 | 3 | 0 | x | 0 | 1 | 1 | LOGIC 0 - GND | I | A1 | 13 | 0 | x | 0 | 1 | 1 | |
| TO RAM CE | O | Y0 | 4 | 1 | 1 | 1 | 1 | 0 | O | Y0 | 12 | 1 | 1 | 1 | 1 | 0 | ||
| TO FLASH CE | O | Y1 | 5 | 1 | 1 | 1 | 0 | 1 | TO FLASH ROE_S | O | Y1 | 11 | 1 | 1 | 1 | 0 | 1 | |
| O | Y2 | 6 | O | Y2 | 10 | 1 | 1 | 0 | 1 | 1 | ||||||||
| O | Y3 | 7 | O | Y3 | 9 | 1 | 0 | 1 | 1 | 1 |
Conclusion
It has been a long journey to get to this point, but we are pleased to report that a hardware solution has been found.
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New cards will be modified with these changes.
512K Flash Modifications
| Pin | Pin | Instruction | Pin | |||
|---|---|---|---|---|---|---|
| Cut track (ROE) underside from pin 24 | U3 | 24 | 512K FLASH | |||
| U4 | 14 | 15 | Lift up pins DO NOT CONNECT TO PCB | |||
| U4 | 14 | A19 - Connect to | U4 | 2 | ||
| U4 | 15 | ROE - Connect to | U1 | 37 | 1M FLASH | |
| U4 | 11 | ROE_S Connect to | U3 | 24 | 512K FLASH |
1M Flash Modifications
| Pin | Pin | Instruction | Pin | |||
|---|---|---|---|---|---|---|
| Cut track (ROE) on top going to | U1 | 37 | 1M FLASH | |||
| U4 | 4 | 5 | Lift up pins DO NOT CONNECT TO PCB | |||
| U4 | 14 | 15 | Lift up pins DO NOT CONNECT TO PCB | |||
| U4 | 14 | (SE1) CE - Connect to | U4 | 1 | ||
| U4 | 15 | ROE - Connect to | U3 | 24 | 512K FLASH | |
| U4 | 11 | ROE_S Connect to | U1 | 37 | 1M FLASH |