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Initially it was decided to protect the top 256K of the Flash chip, where OZ 4.7 is, but it was found that if that area was protected, the Z88 would only see 256K of Flash with no File Area. Using a trial and error technique, it was found by adopting the following connection list
Choosing the output
Using the above truth table was difficult. Connecting the other inputs to the desired state i.e.
- ROE to E (Pin 15)
- Vcc to A0 (Pin 14) for A19 high
- Vcc to A1 (Pin 13) for logic 1
The output was Y3 (Pin 9). It passed through the signal. The other 3 were high. Connecting MA19 and Vcc afterwards, the card worked perfectly.
This procedure was repeated for
- GND to A1 (Pin 13) for logic 0
The output was Y1 (Pin 11).
This was the final result as it would allow the Enable signal from the Z88 to be gated into the logic as well.
512K FLASH PROTECTED & 512 RAM
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Connection List
| I/O | PIN No | I/O | PIN No | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| FROM Z88 CESE1 | I | E | 1 | 0 | 1 | 0 | 0 | 0 | FROM Z88 ROE | I | E | 15 | 0 | 1 | 0 | 0 | 0 | |
| FROM Z88 A19 | I | A0 | 2 | 0 | x | 1 | 0 | 1 | FROM Z88 A19 | I | A0 | 14 | 0 | x | 1 | 0 | 1 | |
| LOGIC 0 - 0v | I | A1 | 3 | 0 | x | 0 | 1 | 1LOGIC 0 - GND | FROM Z88 SE1 | I | A1 | 13 | 0 | x | 0 | 1 | 1 | |
| TO RAM CE | O | Y0 | 4 | 1 | 1 | 1 | 1 | 0 | O | Y0 | 12 | 1 | 1 | 1 | 1 | 0 | ||
| TO FLASH CE | O | Y1 | 5 | 1 | 1 | 1 | 0 | 1 | TO FLASH ROE_S | O | Y1 | 11 | 1 | 1 | 1 | 0 | 1 | |
| O | Y2 | 6 | O | Y2 | 10 | 1 | 1 | 0 | 1 | 1 | ||||||||
| O | Y3 | 7 | O | Y3 | 9 | 1 | 0 | 1 | 1 | 1 |
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- The chip select of the decoder remains unchanged.
This selects the RAM Chip Enable when A19 is low and the FLASH Chip Enable when A19 is high. - The FLASH chip only uses its Chip Enable when it is read, like a ROM.
The second independent part of the decoder does a similar function to the FLASH chip like the first, by only enabling its Output Enable signal with ROE, when A19 is high and Card Enable is low. This means that when the on board RAM is accessed, or the card is no longer enabled, the FLASH chip is no longer able to write to the data bus.
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New cards will be modified with these changes.
512K Flash Modifications
| Pin | Pin | Pin | Instruction | Pin | |||
|---|---|---|---|---|---|---|---|
| Cut track (ROE) underside from pin 24 | U3 | 24 | 512K FLASH | ||||
| U4 | 13 | 14 | 15 | Lift up pins DO NOT CONNECT TO PCB | |||
| U4 | 13 | (SE1) CE - Connect to | U4 | 1 | |||
| U4 | 14 | A19 - Connect to | U4 | 2 | |||
| U4 | 15 | ROE - Connect to | U1 | 37 | 1M FLASH | ||
| U4 | 11 | ROE_S Connect to | U3 | 24 | 512K FLASH |
1M Flash Modifications
| Pin | Pin | Pin | Instruction | Pin | |||
|---|---|---|---|---|---|---|---|
| Cut track (ROE) on top going to | U1 | 37 | 1M FLASH | ||||
| U4 | 4 | 5 | Lift up pins DO NOT CONNECT TO PCB | ||||
| U4 | 13 | 14 | 15 | Lift up pins DO NOT CONNECT TO PCB | |||
| U414 | 13 | (SE1) CE - Connect to | U4 | 1 | |||
| U4 | 14 | Connect to Vcc | |||||
| U4 | 15 | ROE - Connect to | U3 | 24 | 512K FLASH | ||
| U4 | 11 | ROE_S Connect to | U1 | 37 | 1M FLASH |
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