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Introduction

Adding 2 OR, dual logic gates to the design, proved is proving to be cumbersome. It became is a 6 chip design, with the OR gates being a slightly larger chip size. These became are difficult to fit within the 16 pin DIL footprint.

This design was discontinued, but the workings are listed in this documentis currently being laid out on a 4 layer PCB.

Choosing the DECODER and DUAL TWO-INPUT POSITIVE-OR GATE chips

The decoder chip has already been proved on the Z88 design.
Looking through the data sheets for a Texas Instruments VC1 chip found the following timings and package details:-

Part NoChipManufacture/Speed nSPackageDrawingmmPrice


DistributorMax

Pad PitchPad WidthLength
1741279

SN74LVC1G139DCTR

Ti<2.5SM8DCT0.650.34.25$ 0.69

SN74LVC1G139DCUT DecoderTi / Farnell<2.5VSSOPDCU0.50.253.20£0.404
1741279SN74LVC2G32QDCURQ1Ti<2.5SM8DCT0.650.34.25$ 0.55

SN74LVC2G32DCTR  OR Gate

Ti / Farnell<2.5SSOP-8DCT0.650.304.25£0.377

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If a full 74xx139 chip is required it can be either be

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used on its own with pins, plugged into a 16 pin DIL socket on the board where the original 74xx139 was..

Headers and Sockets

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