Introduction

Adding 2 OR, dual logic gates to the design, is proving to be cumbersome. It is a 6 chip design, with the OR gates being a slightly larger chip size. These are difficult to fit within the 16 pin DIL footprint.

This design is currently being laid out on a 4 layer PCB.

Choosing the DECODER and DUAL TWO-INPUT POSITIVE-OR GATE chips

The decoder chip has already been proved on the Z88 design.
Looking through the data sheets for a Texas Instruments VC1 chip found the following timings and package details:-

Part No	Chip	Manufacture/	Speed nS	Package	Drawing	mm			Price
		Distributor	Max			Pad Pitch	Pad Width	Length
1741279	SN74LVC1G139DCTR	Ti	<2.5	SM8	DCT	0.65	0.3	4.25	$ 0.69
	SN74LVC1G139DCUT Decoder	Ti / Farnell	<2.5	VSSOP	DCU	0.5	0.25	3.20	£0.404
1741279	SN74LVC2G32QDCURQ1	Ti	<2.5	SM8	DCT	0.65	0.3	4.25	$ 0.55
	SN74LVC2G32DCTR OR Gate	Ti / Farnell	<2.5	SSOP-8	DCT	0.65	0.30	4.25	£0.377

The 2 input positive display or gates fast times.

Here are the chips that have been chosen:-

PART NUMBER	PACKAGE	BODY SIZE (NOM)
SN74LVC1G139DCT	SM8 (8)	2.95 mm × 2.80 mm

PART NUMBER	PACKAGE	BODY SIZE (NOM)
SN74LVC2G32QDCURQ1	VSSOP (8)	2.30 mm × 2.00 mm

Full Data Sheets for SN74LVC1G139DCT and SN74LVC2G32

This chip provides the logic for the /CE signal.

Circuit Description

There are 2 inputs A and B. The /CE signal enables the chip.

Logic Lab Test v Truth Table

The decoder logic and OR gates were checked against the Simplified Schematic with thanks to http://www.neuroproductions.be/logic-lab/ for the simulator.

Inputs Enable Select				Outputs
	/CE	A	B	/Y3	/Y2	/Y1	/Y0
00	0	0	0	1	1	1	0
01	0	0	1	1	1	0	1
02	0	1	0	1	0	1	1
03	0	1	1	0	1	1	1
	1	X	X	1	1	1	1

	/CE = 0	/CE = 1
00
01
02
03

The eight combinations all agree.

http://www.neuroproductions.be/logic-lab/index.php?id=64582

http://www.neuroproductions.be/logic-lab/index.php?id=64583

The simulator file may be used and viewed at

http://www.neuroproductions.be/logic-lab/index.php?id=64758

Circuit Diagram using a 2-to-4 Line Decoder and 2 Dual OR Chips.

To be Updated wrong circuit displayed

All the components required are fitted on a single card.

Testing the Circuit

The 2 to 4 line decoder has been tested using /CE to select the top half of the device. Now the /CE signal needs to be tested using the two NAND gates connected to the output of Y0 and Y1. A1 is connected to GND so that only Y0 and Y1 are used.

2-to-4 Line Decoder and 2 Dual OR Chips

If a full 74xx139 chip is required it can be used on its own with pins, plugged into a 16 pin DIL socket on the board where the original 74xx139 was..

Headers and Sockets

	Photo	Dia hole mm
8 way header		1.00	http://uk.farnell.com/te-connectivity-amp/826629-8/header-1row-8way/dp/3418364	£0.596
		0.90	http://uk.farnell.com/te-connectivity-amp/215297-8/socket-vertical-1row-8way/dp/3419101	£0.54

Building the circuit on a breadboard externally

Components required

1 SSOP8 IC adaptor was obtained in addition to the DUAL TWO-INPUT POSITIVE-OR GATE chip.
This circuit could now be bread-boarded and tested as a 1/4 139 as the other 3/4 of the chip is the same logic.

Footprint is different for the Decoder and NAND gates

The decoder and NAND gates chips have different footprints.0.5 mm pitch for the decoder and 0.65 mm pitch for the NAND Gates.

This photo needs to be replaced with one showing the Decoder and the Dual NAND gates.

The four signal and power lines can be seen connecting the card to the breadboard.

This picture needs to be replaced.

The Games play without crashing.

Oscilloscope Readings

(This picture needs replacing)

This produced the signals required.

This trace shows the Flash chip being selected (/CE1) in 3nS.

The RAM (/CE) would be the same timings.

Signals not the same abbreviations as the circuit

The names of the signals on the scope are not all the same as shown in the circuit.

Signal	Scope	Circuit
A19	A19	A19
/CE1	_CE1	/CE1
/CE0	_CE	/CE0

Printed Circuit Board

Main points

Fast low power decoder used
Fast low power NAND gates used
4 Layer board used
All fits in a 16 DIL footprint

4 Layer Board

Signal lines are used on all 4 layers. This is because all eight terminals are used and it is the only way to get the connections out from the middle of the chip. Connecting power to the chips is easier as well using stub connections.

Power Allocation
top copper	GND
inner 1	GND
inner 2	Vcc
bottom	GND

Provisional Layout

To be updated when completed

The 7 layers

Here are the layers printed on A4 sheets. The board is small, zooming in is generally helpful.

To be done