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This was thought to be due to an intermittent timing error from the decode chip CD74HCT139 which switches between the RAM and Flash chip but after the Z88 Hardware Investigation, it has been discovered to be a misunderstanding by both the hardware and software engineers on how to write faultlessly to the flash chip. This has only affected a few users, i.e. those who play games in RAM or who do repetitive writing to the flash card. The majority of users have not reported any problems.
Object
Although the best solution would be a software upgrade to OZ 4.7 allowing users to update their cards, it has been decided to see if by changing the hardware the same result may be achieved. See Writing to Flash Chips for a full explanation of what needs to be fixed. NOTE: This needs to be updated with the results found here.
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| I/O | PIN No | I/O | PIN No | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| FROM Z88 SE1 | I | E | 1 | 1 | 0 | 0 | 0 | 0 | FROM Z88 ROE | I | E | 15 | 1 | 0 | 0 | 0 | 0 | |
| FROM Z88 MA19 | I | A0 | 2 | X | 1 | 0 | 1 | 0 | FROM Z88 SE1 | I | A0 | 14 | X | 1 | 0 | 1 | 0 | |
| LOGIC 0 - 0v | I | A1 | 3 | X | 1 | 1 | 0 | 0 | LOGIC 0 - 0v | I | A1 | 13 | X | 1 | 1 | 0 | 0 | |
| TO RAM CE | O | Y0 | 4 | 1 | 1 | 1 | 1 | 0 | TO FLASH ROE_S | O | Y0 | 12 | 1 | 1 | 1 | 1 | 0 | |
| TO FLASH CE | O | Y1 | 5 | 1 | 1 | 1 | 0 | 1 | O | Y1 | 11 | 1 | 1 | 1 | 0 | 1 | ||
| O | Y2 | 6 | 1 | 1 | 0 | 1 | 1 | O | Y2 | 10 | 1 | 1 | 0 | 1 | 1 | |||
| O | Y3 | 7 | 1 | 0 | 1 | 1 | 1 | O | Y3 | 9 | 1 | 0 | 1 | 1 | 1 |
Conclusion
It has been a long journey to get to this point, but we are pleased to report Further testing will be done before reporting that a hardware solution has been found.
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- The chip select of the decoder remains unchanged.
This selects the RAM Chip Enable when A19 is low and the FLASH Chip Enable when A19 is high. - The FLASH chip only uses its Chip Enable when it is read, like a ROM.
The second independent part of the decoder does a similar function to the FLASH chip like the first, by only enabling its Output Enable signal with ROE, when A19 is high and Card Enable is low. This means that when the on board RAM is accessed, or the card is no longer enabled, the FLASH chip is no longer able to write to the data bus. - The extra circuitry does in effect the same thing as the chip enable, but gates the Output Enable signal. This prevents the flash chip from writing to the data bus when it is not selected.
POE & ROE
Splitting these two signals on the 512K/512K Flash/RAM card has made no difference. There are more cycles generated on the POE signal to refresh the RAM, but it was found that even Cambridge are using the ROE signal for their RAMs so it is proposed to leave ROE to Output Enable the FLASH and RAM as before.
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| Pin | Pin | Pin | Instruction | Pin | |||
|---|---|---|---|---|---|---|---|
| Cut track (ROE) underside from pin 24 | U3 | 24 | 512K FLASH | ||||
| U4 | 13 | 14 | 15 | Lift up pins DO NOT CONNECT TO PCB | |||
| U4 | 13 | A19 - Connect to | U4 | 2 | |||
| U4 | 14 | (SE1) CE - Connect to | U4 | 1 | |||
| U4 | 15 | ROE - Connect to VIA | |||||
| U4 | 10 | ROE_S Connect to | U1 | 37 | 512K FLASH OE |
1M Flash Modifications
| Pin | Pin | Pin | Instruction | Pin | |||
|---|---|---|---|---|---|---|---|
| Cut track (ROE) on top going to | U1 | 37 | 1M FLASH | ||||
| U4 | 4 | 5 | Lift up pins DO NOT CONNECT TO PCB | ||||
| U4 | 14 | 15 | Lift up pins DO NOT CONNECT TO PCB | ||||
| U4 | 13 | REMAINS ON GND | |||||
| U4 | 14 | (SE1) CE - Connect to | U4 | 1 | |||
| U4 | 15 | ROE - Connect to | U3 | 24 | 512K FLASH | ||
| U4 | 12 | ROE_S Connect to | U1 | 37 | 1M FLASH |
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