Introduction
The Z88 Flash/RAM card has been working for several years now. When OZ 4.6 was introduced, allowing applications to be run in RAM, some games failed to run.
| Standard Version | Modified Turbo Version |
|---|---|
|
|
This was thought to be due to an intermittent timing error from the decode chip CD74HCT139 which switches between the RAM and Flash chip but after the Z88 Hardware Investigation, it has been discovered to be a misunderstanding by both the hardware and software engineers on how to write faultlessly to the flash chip.
Object
Although the best solution would be a software upgrade to OZ 4.7 allowing users to update their cards, it has been decided to see if by changing the hardware the same result may be achieved. See Writing to Flash Chips for a full explanation of what needs to be fixed.
The object of this exercise is to see if by redefining the address map and by hardware prevent the flash chip from writing to the data bus when it is running OZ 4.7.
It has already been proved that if OZ 4.7 is run in a 256K EPROM card, the application runs faultlessly. This is because the code that writes to the Flash chip is ignored by the EPROM. There are several ways of achieving the same effect by changing the address mapping in the 1M space available on the card.
| EPROM | FLASH | RAM | |||||||
|---|---|---|---|---|---|---|---|---|---|
| OZ 4.7 | FILES | PROTECTED | FILES | CE | A19 | A18 | ROE | ||
| Replace Flash with EPROM 1 | 256K | 768K | X | X | X | ||||
| Replace Flash with EPROM 2 | 256K | 256K | 512K | X | X | ||||
| Protect Flash | 256K | 256K | 512K | X | X | X | X | ||
| OPTION 4 | |||||||||
Decoder Connections
The decode chip used, is repeated twice in the same device. The first part does the 512K/512K Decode (as before) whilst the unused part is used for the changes.
In all cases, the input pins of the unused part (Pins 13, 14 & 15), need to be isolated as they have been connected to GND.
Replace Flash with EPROM 1
256K EPROM 768 RAM
| CE | A19 | A18 | |
|---|---|---|---|
| 256K EPROM | 0 | 1 | 1 |
| 768K RAM | 0 | 0 | 0 |
Connection List
| I/O | PIN No | I/O | PIN No | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| CE | I | E | 1 | 0 | 1 | 0 | 0 | 0 | CEFLS | I | E | 15 | 0 | 1 | 0 | 0 | 0 | |||
| A19 | I | A0 | 2 | 0 | x | 1 | 0 | 1 | A19 | I | A0 | 14 | 0 | x | 1 | 0 | 1 | |||
| 0v | I | A1 | 3 | 0 | x | 0 | 1 | 1 | A18 | I | A1 | 13 | 0 | x | 0 | 1 | 1 | |||
| CERA | O | Y0 | 4 | 1 | 1 | 1 | 1 | 0 | CERA | O | Y0 | 12 | 1 | 1 | 1 | 1 | 0 | CE TO RAM | ||
| CEFLS | O | Y1 | 5 | 1 | 1 | 1 | 0 | 1 | CEFL | O | Y1 | 11 | 1 | 1 | 1 | 0 | 1 | CE TO EPROM |
Replace Flash with EPROM 2
512K EPROM 512 RAM
NO CHANGE TO DECODE CHIP
| PIN No | |||||||
|---|---|---|---|---|---|---|---|
| CE | E | 1 | 0 | 1 | 0 | 0 | 0 |
| A19 | A0 | 2 | 0 | x | 1 | 0 | 1 |
| 0v | A1 | 3 | 0 | x | 0 | 1 | 1 |
| CERA | Y0 | 4 | 1 | 1 | 1 | 1 | 0 |
| CEFL | Y1 | 5 | 1 | 1 | 1 | 0 | 1 |
Protect Flash
256K FLASH PROTECTED, 256K FLASH & 512 RAM
| CE | A19 | A18 | ROES | |
|---|---|---|---|---|
| 256K FLASH PROTECTED | X | 1 | 1 | 1 |
| 256K FLASH | 1 | 1 | 0 | ROE |
| 512K RAM | 0 | 0 |
Connection List
| I/O | PIN No | I/O | PIN No | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| CE | I | E | 1 | 0 | 1 | 0 | 0 | 0 | ROE | I | E | 15 | 0 | 1 | 0 | 0 | 0 | |||
| A19 | I | A0 | 2 | 0 | x | 1 | 0 | 1 | A19 | I | A0 | 14 | 0 | x | 1 | 0 | 1 | |||
| 0v | I | A1 | 3 | 0 | x | 0 | 1 | 1 | A18 | I | A1 | 13 | 0 | x | 0 | 1 | 1 | |||
| CERA | O | Y0 | 4 | 1 | 1 | 1 | 1 | 0 | O | Y0 | 12 | 1 | 1 | 1 | 1 | 0 | ||||
| CEFL | O | Y1 | 5 | 1 | 1 | 1 | 0 | 1 | O | Y1 | 11 | 1 | 1 | 1 | 0 | 1 | ROE_S TO FLASH |
BELOW THIS NOTICE IS IRRELEVANT
This document has been copied. Rather than deleting the unwanted to start with, deletion and changes are done as the author works down the page.
NAND Gate Build
Building the circuit on a breadboard externally
5 NAND gates were used to test whether a faster time could be achieved with the Z88.
Results
The latest software was tried again in a standard 512K/512K Flash/RAM Card and Vic could not make the games software go wrong. The prototype board was packed and sent to Mr T who had a failing Z88 and 512K/512K Flash/RAM Card. He confirmed that it was the decoder chip that was causing the fault and suggested that another decoder could be found.
DECODER Chip Build
Building the circuit on a breadboard externally
Using 5 NAND Gates to prove that there is a hardware problem was very useful, but for a production run using a single 2-to-4 Line Decoder chip to replace them is the next step.
This circuit could now be bread-boarded and tested outside the Z88 card case again.
The four signal and power lines can be seen connecting the card to the breadboard.
Results
The Games played without crashing. The PCB could now be designed.
Z88 Turbo Card produced
It has been proved that the decode chip in the Z88 Flash/RAM card is too slow. Existing users who wish to run applications in RAM will need their cards modified with the chip being replaced with this card.
Full 74xx139 Version Build Concept
A new opportunity or a waste of time?
The decoder chip above works. It changes the timing from 10 to 3nS and replaces 1/4 of the 74139 in the Z88 design. Is there a demand for a full 74xx139 replacement card?
For the full version, adding 2 OR, dual logic gates to the outputs adds the /CE signal to the design. The challenge is to
- fit 6 chips into a 16 pin DIL footprint
- establish whether there is a demand
SMD or DIL Footprint?
| 16 pin DIL | 16 pin SO 16 |
|---|---|
|
|
| |
Using the Z88 Turbo Card fitting pins or wires to connect the 74xx139 Card piggybacked both footprints may be accommodated. This has proved to be impractical. Another design needs to be considered if required perhaps using a slot across the middle to connect the SO16 footprint to the card.
Build 74xx139 on a 16 pin DIL footprint
This should be possible, 3 chips on each side of the PCB with 2 rows of 8 pins on either side.
Demand or not?
Once the PCB design has been completed, it can be costed and this concept can be floated.
A decision may be made then whether to proceed with manufacture the PCB or not. It could be used in legacy equipment to see if it improved the performance. There could also be different options.
- card only
- card and components (to build)
- fully built
It will definitely not be able to compete on price, as it will cost more than 10p.
Building the circuit on a breadboard externally
Needs to be done
A test needs to be done to test the functionality of the NAND gate using the /CE signal.
The four signal and power lines can be seen connecting the card to the breadboard.
Results
The results need to be reported.
Printed Circuit Board
74xx139 DIL Card
To be done
There are two functions for this card.
- The DIL 16 pads have holes through them allowing wires to be soldered to DIL 16 pads on another card.
- When used with the Z88 Flash/RAM card, it can be used with a SO 16 footprint. 16 pins or wires need to be soldered so that the DIL chip or converter card can be piggy backed on top with 2 off SIL sockets.
74xx139 to be produced or not
Depends on response.