Introduction
The Z88 Flash/RAM card has been working for several years now. When OZ 4.6 was introduced, allowing applications to be run in RAM, some games failed to run.
Standard Version | Modified Turbo Version |
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This was thought to be due to an intermittent timing error from the decode chip CD74HCT139 which switches between the RAM and Flash chip but after the Z88 Hardware Investigation, it hasĀ been discovered to be a misunderstanding by both the hardware and software engineers on how to write faultlessly to the flash chip.
Object
Although the best solution would be a software upgrade to OZ 4.7 allowing users to update their cards, it has been decided to see if by changing the hardware the same result may be achieved. See Writing to Flash Chips for a full explanation of what needs to be fixed.
The object of this exercise is to see if by redefining the address map and by hardware prevent the flash chip from writing to the data bus when it is running OZ 4.7.
It has already been proved that if OZ 4.7 is run in a 256K EPROM card, the application runs faultlessly. This is because the code that writes to the Flash chip is ignored by the EPROM. There are several ways of achieving the same effect by changing the address mapping in the 1M space available on the card.
EPROM | FLASH | RAM | |||||||
---|---|---|---|---|---|---|---|---|---|
OZ 4.7 | FILES | PROTECTED | FILES | CE | A19 | A18 | ROE | ||
Replace Flash with EPROM 1 | 256K | 768K | X | X | X | ||||
Replace Flash with EPROMĀ 2 | 256K | 256K | 512K | X | X | ||||
Protect Flash | 256K | 256K | 512K | X | X | X | X |
Decoder Connections
The decode chip used, is repeated twice in the same device. The first part does the 512K/512K Decode (as before) whilst the unused part is used for the changes.
In all cases, the input pins of the unused part (Pins 13, 14 & 15), need to be isolated as they have been connected to GND.
Replace Flash with EPROM 1
256K EPROM 768 RAM
CE | A19 | A18 | |
---|---|---|---|
256K EPROM | 0 | 1 | 1 |
768K RAM | 0 | 0 | 0 |
Connection List
I/O | PIN No | I/O | PIN No | |||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CE | I | E | 1 | 0 | 1 | 0 | 0 | 0 | CEFLS | I | E | 15 | 0 | 1 | 0 | 0 | 0 | |||
A19 | I | A0 | 2 | 0 | x | 1 | 0 | 1 | A19 | I | A0 | 14 | 0 | x | 1 | 0 | 1 | |||
0v | I | A1 | 3 | 0 | x | 0 | 1 | 1 | A18 | I | A1 | 13 | 0 | x | 0 | 1 | 1 | |||
CERA | O | Y0 | 4 | 1 | 1 | 1 | 1 | 0 | CERA | O | Y0 | 12 | 1 | 1 | 1 | 1 | 0 | CE TO RAM | ||
CEFLS | O | Y1 | 5 | 1 | 1 | 1 | 0 | 1 | CEFL | O | Y1 | 11 | 1 | 1 | 1 | 0 | 1 | CE TO EPROM |
Replace Flash with EPROM 2
512K EPROM 512 RAM
NO CHANGE TO DECODE CHIP
PIN No | |||||||
---|---|---|---|---|---|---|---|
CE | E | 1 | 0 | 1 | 0 | 0 | 0 |
A19 | A0 | 2 | 0 | x | 1 | 0 | 1 |
0v | A1 | 3 | 0 | x | 0 | 1 | 1 |
CERA | Y0 | 4 | 1 | 1 | 1 | 1 | 0 |
CEFL | Y1 | 5 | 1 | 1 | 1 | 0 | 1 |
Protect Flash
256K FLASH PROTECTED, 256K FLASH & 512 RAM
CE | A19 | A18 | ROES | |
---|---|---|---|---|
256K FLASH PROTECTED | X | 1 | 1 | 1 |
256K FLASH | 1 | 1 | 0 | ROE |
512K RAM | 0 | 0 |
Connection List
I/O | PIN No | I/O | PIN No | |||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CE | I | E | 1 | 0 | 1 | 0 | 0 | 0 | ROE | I | E | 15 | 0 | 1 | 0 | 0 | 0 | |||
A19 | I | A0 | 2 | 0 | x | 1 | 0 | 1 | A19 | I | A0 | 14 | 0 | x | 1 | 0 | 1 | |||
0v | I | A1 | 3 | 0 | x | 0 | 1 | 1 | A18 | I | A1 | 13 | 0 | x | 0 | 1 | 1 | |||
CERA | O | Y0 | 4 | 1 | 1 | 1 | 1 | 0 | O | Y0 | 12 | 1 | 1 | 1 | 1 | 0 | ||||
CEFL | O | Y1 | 5 | 1 | 1 | 1 | 0 | 1 | O | Y1 | 11 | 1 | 1 | 1 | 0 | 1 | ROE_S TO FLASH |
Decoder Tests
The decode circuits were built on a breadboard externally using DIL instead of using the SMD used on the card for easier testing.
16 pin DIL | 16 pin SO 16 |
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