The decoder chip above works. It replaces 1/4 of the 74139 for the Z88 design.
For the full version, adding 2 OR, dual logic gates to the outputs enables the /CE signal to the design.
Choosing the DUAL TWO-INPUT POSITIVE-OR GATE chip
Looking through the data sheets for a Texas Instruments VC1 chip found the following timings:-
| Part No | Chip | Manufacture | Speed nS | Package | Price | |||
|---|---|---|---|---|---|---|---|---|
| Min | Typ | Max | ||||||
| 1741279 | SN74LVC2G32QDCURQ1 | Ti | <2.5 | SM8 | $ 0.55 | |||
| SN74LVC1G139DCUT | Ti / Farnell | <2.5 | VSSOP | £0.404 | ||||
The 2-to-4 Line Decoder display fast times.
Here is the chip that has been chosen:-
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Full Data Sheet for SN74LVC2G32-Q1 DUAL TWO-INPUT POSITIVE-OR GATE & Timing
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This chip provides the logic for the /CE signal.
Circuit Description
There are 2 inputs A and B. The /CE signal enables the chip.
Logic Lab Test v Truth Table
The logic was checked against the Simplified Schematic with thanks to http://www.neuroproductions.be/logic-lab/ for the simulator.
| Inputs Enable Select | Outputs | ||||||
|---|---|---|---|---|---|---|---|
| /CE | A | B | /Y3 | /Y2 | /Y1 | /Y0 | |
| 00 | 0 | 0 | 0 | 1 | 1 | 1 | 0 |
| 01 | 0 | 0 | 1 | 1 | 1 | 0 | 1 |
| 02 | 0 | 1 | 0 | 1 | 0 | 1 | 1 |
| 03 | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
| 1 | X | X | 1 | 1 | 1 | 1 | |
| /CE = 0 | /CE = 1 | |
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00 |
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01 |
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02 |
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03 |
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The eight combinations all agree.
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Building the circuit on a breadboard externally
Components required
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2 MSOP-8 IC adaptors were obtained in addition to the DUAL TWO-INPUT POSITIVE-OR GATE chips.
This circuit could now be bread-boarded and tested.
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