Introduction

The decoder chip works. It replaces 1/4 of the 74139 for the Z88 design.

Two designs were considered for the full 74139 version

• adding 2 OR, dual logic gates to the outputs to enable the /CE signal to the design.
• or using 4 decoder chips.

Adding 2 OR, dual logic gates, proved to be cumbersome. It became a 6 chip design, with the OR gates being a slightly larger chip size. This became difficult to fit within the 16 pin DIL footprint.

If the decoder chip replaced 1/4 of the 74139, could 4 of them do the job? Unfortunately no matter how hard I tried, I could not make the logic to work.

Choosing the DECODER chips

Looking through the data sheets for a Texas Instruments VC1 chip found the following timings and package details:-

The same decoder chip has been chosen.

Here is the chip that has been chosen:-

Full Data Sheets for SN74LVC1G139DCT

This chip provides the logic for the /CE signal.

Circuit Description

There are 2 inputs A and B. The /CE signal enables the chip.

Logic Lab Test v Truth Table

The decoder logic and OR gates were checked against the Simplified Schematic with thanks to http://www.neuroproductions.be/logic-lab/ for the simulator.

The eight combinations all agree.

http://www.neuroproductions.be/logic-lab/index.php?id=64582

http://www.neuroproductions.be/logic-lab/index.php?id=64583

The simulator file may be used and viewed at

http://www.neuroproductions.be/logic-lab/index.php?id=64758

Trying to get this to work

http://www.neuroproductions.be/logic-lab/index.php?id=67507

Circuit Diagram using a 2-to-4 Line Decoder and 2 Dual OR Chips.

To be Updated wrong circuit displayed

All the components required are fitted on a single card.

Testing the Circuit

The 2 to 4 line decoder has been tested using /CE to select the top half of the device. Now the /CE signal needs to be tested using the two NAND gates connected to the output of Y0 and Y1. A1 is connected to GND so that only Y0 and Y1 are used.

2-to-4 Line Decoder and 2 Dual OR Chips

If a full 74xx139 chip is required it can be either be

• piggy backed (using the DIL connections) to Z88 Turbo card if the 16 Pin SOIC footprint is required or
• used on its own with pins, plugged into a 16 pin DIL socket on the board where the original 74xx139 was..

Headers and Sockets

Building the circuit on a breadboard externally

Components required

1 SSOP8 IC adaptor was obtained in addition to the DUAL TWO-INPUT POSITIVE-OR GATE chip. 
This circuit could now be bread-boarded and tested as a 1/4 139 as the other 3/4 of the chip is the same logic.

This photo needs to be replaced with one showing the Decoder and the Dual NAND gates.

The four signal and power lines can be seen connecting the card to the breadboard.

This picture needs to be replaced.

The Games play without crashing.

Oscilloscope Readings

(This picture needs replacing)

This produced the signals required.

This trace shows the Flash chip being selected (/CE1) in 3nS.

The RAM (/CE) would be the same timings.

Printed Circuit Board

Main points

• Fast low power decoder used
• Fast low power NAND gates used
• 4 Layer board used
• All fits in a 16 DIL footprint

4 Layer Board

Signal lines are used on all 4 layers. This is because all eight terminals are used and it is the only way to get the connections out from the middle of the chip. Connecting power to the chips is easier as well using stub connections.

Provisional Layout

To be updated when completed

The 7 layers

Here are the layers printed on A4 sheets. The board is small, zooming in is generally helpful.

To be done