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Introduction

The decoder chip works. It replaces 1/4 of the 74139 for the Z88 design.

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If the decoder chip replaced 1/4 of the 74139, could 4 of them do the job? Unfortunately no matter how hard I tried, I could not make the logic to work.

Choosing the DECODER

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chips

Looking through the data sheets for a Texas Instruments VC1 chip found the following timings and package details:-

DCT
Part NoChipManufacture/Speed nSPackageDrawingmmPrice


DistributorMax

Pad PitchPad WidthLength
1741279

SN74LVC1G139DCTR

Ti<2.5SM8DCT0.650.34.25$ 0.69

SN74LVC1G139DCUT DecoderTi / Farnell<2.5VSSOPDCU0.50.253.20£0.4041741279SN74LVC2G32QDCURQ1Ti<2.5SM80.650.34.25$ 0.55

SN74LVC2G32DCTR  OR Gate

Ti / Farnell<2.5SSOP-8DCT0.650.304.25£0.377

The 2 input positive display or gates fast times.

Here are the chips that have The same decoder chip has been chosen.

Here is the chip that has been chosen:-


PART NUMBER


PART NUMBERPACKAGEBODY SIZE (NOM)
SN74LVC1G139DCTSM8 (8)2.95 mm × 2.80 mm

Image Removed

PACKAGEBODY SIZE (NOM)
SN74LVC2G32QDCURQ1VSSOP (8)2.30 mm × 2.00 mm


Full Data Sheets for SN74LVC1G139DCT

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View file
namesn74lvc1g139.pdf
pageTurbocharging the decode chip
height250

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This chip provides the logic for the /CE signal.

Circuit Description

There are 2 inputs A and B. The /CE signal enables the chip.

Logic Lab Test v Truth Table

The decoder logic and OR gates were checked against the Simplified Schematic with thanks to http://www.neuroproductions.be/logic-lab/ for the simulator.

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http://www.neuroproductions.be/logic-lab/index.php?id=64758

Trying to get this to work

http://www.neuroproductions.be/logic-lab/index.php?id=67507

Circuit Diagram using a 2-to-4 Line Decoder and 2 Dual OR Chips.

To be Updated wrong circuit displayed

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All the components required are fitted on a single card.

Testing the Circuit

The 2 to 4 line decoder has been tested using /CE to select the top half of the device. Now the /CE signal needs to be tested using the two NAND gates connected to the output of Y0 and Y1. A1 is connected to GND so that only Y0 and Y1 are used.

2-to-4 Line Decoder and 2 Dual OR Chips

If a full 74xx139 chip is required it can be either be

  • piggy backed (using the DIL connections) to Z88 Turbo card if the 16 Pin SOIC footprint is required or
  • used on its own with pins, plugged into a 16 pin DIL socket on the board where the original 74xx139 was..

Headers and Sockets



Building the circuit on a breadboard externally

Components required

1 SSOP8 IC adaptor was obtained in addition to the DUAL TWO-INPUT POSITIVE-OR GATE chip. 
This circuit could now be bread-boarded and tested as a 1/4 139 as the other 3/4 of the chip is the same logic.

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The Games play without crashing.

Oscilloscope Readings

(This picture needs replacing)

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Note
titleSignals not the same abbreviations as the circuit

The names of the signals on the scope are not all the same as shown in the circuit.

SignalScopeCircuit
A19A19A19
/CE1_CE1/CE1
/CE0_CE/CE0


Printed Circuit Board

Main points

  • Fast low power decoder used
  • Fast low power NAND gates used
  • 4 Layer board used
  • All fits in a 16 DIL footprint

4 Layer Board

Signal lines are used on all 4 layers. This is because all eight terminals are used and it is the only way to get the connections out from the middle of the chip. Connecting power to the chips is easier as well using stub connections.

Power Allocation
top copperGND
inner 1GND
inner 2Vcc
bottomGND

Provisional Layout

To be updated when completed

The 7 layers

Here are the layers printed on A4 sheets. The board is small, zooming in is generally helpful.

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