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Introduction

The decoder chip above works. It replaces 1/4 of the 74139 for the Z88 design.

For Two designs were considered for the full 74139 version,

• adding 2 OR, dual logic gates to the outputs

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• to enable the /CE signal to the design.
• or using 4 decoder chips.

Adding 2 OR, dual logic gates, proved to be cumbersome. It became a 6 chip design, with the OR gates being a slightly larger chip size. This became difficult to fit within the 16 pin DIL footprint.

If the decoder chip replaced 1/4 of the 74139, could 4 of them do the job? Unfortunately no matter how hard I tried, I could not make the logic to work.

Choosing the

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DECODER chips

Looking through the data sheets for a Texas Instruments VC1 chip found the following timings and package details:-

The 2-to-4 Line Decoder display fast timessame decoder chip has been chosen.

Here is the chip that has been chosen:-

Full Data

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Sheets for SN74LVC1G139DCT

This chip provides the logic for the /CE signal.

Circuit Description

There are 2 inputs A and B. The /CE signal enables the chip.

Logic Lab Test v Truth Table

The decoder logic was and OR gates were checked against the Simplified Schematic with thanks to http://www.neuroproductions.be/logic-lab/ for the simulator.

The eight combinations all agree.

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http://www.neuroproductions.be/logic-lab/index.php?id=64758

Trying to get this to work

http://www.neuroproductions.be/logic-lab/index.php?id=67507

Circuit Diagram using a 2-to-4 Line Decoder and 2 Dual OR Chips.

2-to-4 Line Decoder

Updated 17/11/2016To be Updated wrong circuit displayed

All the components required cannot be are fitted on a single card. The design has been split onto two cards. The first PCB is just for the Z88

Testing the Circuit

The 2 to 4 line decoder has been tested using /CE to select the top half of the device. Now the /CE signal needs to be tested using the two NAND gates connected to the output of Y0 and Y1. A1 is connected to GND so that only Y0 and Y1 are used.

2-to-4 Line Decoder and 2 Dual OR Chips

If a full 74139 74xx139 chip is required another PCB with the extra components it can be either be

• piggy backed (using the DIL connections) to this Z88 Turbo card if the 16 Pin SOIC footprint is required or
• used on its own with pins, plugged into a 16 pin DIL socket on the board where the original 74xx139 was..

Headers and Sockets

Building the circuit on a breadboard externally

Components required

Image Removed

Image Added

Image Modified

2 MSOP-8 IC adaptors were 1 SSOP8 IC adaptor was obtained in addition to the DUAL TWO-INPUT POSITIVE-OR GATE chipsGATE chip. 
This circuit could now be bread-boarded and tested as a 1/4 139 as the other 3/4 of the chip is the same logic.

This photo needs to be replaced with one showing the Decoder and the Dual NAND gates.

The four signal and power lines can be seen connecting the card to the breadboard.

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The Games play without crashing.

Oscilloscope Readings

(This picture needs replacing)

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Printed Circuit Board

2-to-4 Line Decoder

Main points

• Small holes are drilled in the centre of the pads of H1,so that wire links may be used to connect the signals from the 512K/512K card to the PCB.
• The pads of the footprint of the SOT-23-5 have been made longer, to enable easier soldering of the small parts.
• The bottom Left Hand corner of the PCB matches the shape of the 512K/512K Card for easy alignment.

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Main points

• Fast low power decoder used
• Fast low power NAND gates used
• 4 Layer board used
• All fits in a 16 DIL footprint

4 Layer Board

Signal lines are used on all 4 layers. This is because all eight terminals are used and it is the only way to get the connections out from the middle of the chip. Connecting power to the chips is easier as well using stub connections.

Provisional Layout

To be updated when completed

The 7 layers

Here are the layers printed on A4 sheets. The board is small, zooming in is generally helpful.

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