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Introduction
The decoder chip works. It replaces 1/4 of the 74139 for the Z88 design.
For Two designs were considered for the full 74139 version,
- adding 2 OR, dual logic gates to the outputs
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- to enable the /CE signal to the design.
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- or using 4 decoder chips.
Adding 2 OR, dual logic gates, proved to be cumbersome. It became a 6 chip design, with the OR gates being a slightly larger chip size. This became difficult to fit within the 16 pin DIL footprint.
If the decoder chip replaced 1/4 of the 74139, could 4 of them do the job? Unfortunately no matter how hard I tried, I could not make the logic to work.
Choosing the DECODER chips
Looking through the data sheets for a Texas Instruments VC1 chip found the following timings and package details:-
Part No | Chip | Manufacture/ | Speed nS | Package | Drawing | mm | Price | ||||
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Min | Typ | MaxDistributor | Max | Pad Pitch | Pad Width | Length | |||||
1741279 | SN74LVC2G32QDCURQ1SN74LVC1G139DCTR | Ti | <2.5 | SM8 | DCT | 0.65 | 0.3 | 4.25 | $ 0.5569 | ||
SN74LVC1G139DCUT Decoder | Ti / Farnell | <2.5 | VSSOP | DCU | 0.5 | 0.25 | 3.20 | £0.404 |
The 2 input positive display or gates fast timessame decoder chip has been chosen.
Here is the chip that has been chosen:-
| SN74LVC2G32QDCURQ1
| VSSOP
| 30
| 00
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Full Data
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Sheets for SN74LVC1G139DCT
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This chip provides the logic for the /CE signal.
Circuit Description
There are 2 inputs A and B. The /CE signal enables the chip.
Logic Lab Test v Truth Table
The decoder logic and OR gates were checked against the Simplified Schematic with thanks to http://www.neuroproductions.be/logic-lab/ for the simulator.
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http://www.neuroproductions.be/logic-lab/index.php?id=64758
Trying to get this to work
http://www.neuroproductions.be/logic-lab/index.php?id=67507
Circuit Diagram using a 2-to-4 Line Decoder and 2 Dual OR Chips.
To be Updated wrong circuit displayed
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All the components required are fitted on a single card.
Testing the Circuit
The 2 to 4 line decoder has been tested using /CE to select the top half of the device. Now the /CE signal needs to be tested using the two NAND gates connected to the output of Y0 and Y1. A1 is connected to GND so that only Y0 and Y1 are used.
2-to-4 Line Decoder and 2 Dual OR Chips
If a full 74xx139 chip is required it can be either be
- piggy backed (using the DIL connections) to Z88 Turbo card if the 16 Pin SOIC footprint is required or
- used on its own with pins, plugged into a 16 pin DIL socket on the board where the original 74xx139 was..
Headers and Sockets
Photo | Dia hole mm | |||
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8 way header | 1.00 | http://uk.farnell.com/te-connectivity-amp/826629-8/header-1row-8way/dp/3418364 | £0.596 | |
0.90 | http://uk.farnell.com/te-connectivity-amp/215297-8/socket-vertical-1row-8way/dp/3419101 | £0.54 |
Building the circuit on a breadboard externally
Components required
2 MSOP-8 IC adaptors were 1 SSOP8 IC adaptor was obtained in addition to the DUAL TWO-INPUT POSITIVE-OR GATE chipsGATE chip.
This circuit could now be bread-boarded and tested as a 1/4 139 as the other 3/4 of the chip is the same logic.
Info | ||
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The decoder and NAND gates chips have different footprints.0.5 mm pitch for the decoder and 0.65 mm pitch for the NAND Gates. |
This photo needs to be replaced with one showing the Decoder and the Dual NAND gates.
The four signal and power lines can be seen connecting the card to the breadboard.
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The Games play without crashing.
Oscilloscope Readings
(This picture needs replacing)
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Note | ||||||||||||
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The names of the signals on the scope are not all the same as shown in the circuit.
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Printed Circuit Board
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2-to-4 Line Decoder
Main points
- Small holes are drilled in the centre of the pads of H1,so that wire links may be used to connect the signals from the 512K/512K card to the PCB.
- The pads of the footprint of the SOT-23-5 have been made longer, to enable easier soldering of the small parts.
- The bottom Left Hand corner of the PCB matches the shape of the 512K/512K Card for easy alignment.
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Main points
- Fast low power decoder used
- Fast low power NAND gates used
- 4 Layer board used
- All fits in a 16 DIL footprint
4 Layer Board
Signal lines are used on all 4 layers. This is because all eight terminals are used and it is the only way to get the connections out from the middle of the chip. Connecting power to the chips is easier as well using stub connections.
Power Allocation | |
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top copper | GND |
inner 1 | GND |
inner 2 | Vcc |
bottom | GND |
Provisional Layout
To be updated when completed
The 7 layers
Here are the layers printed on A4 sheets. The board is small, zooming in is generally helpful.
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