The decoder chip works. It replaces 1/4 of the 74139 for the Z88 design.
For the full version, adding 2 OR, dual logic gates to the outputs enables the /CE signal to the design.
Choosing the DUAL TWO-INPUT POSITIVE-OR GATE chip
Looking through the data sheets for a Texas Instruments VC1 chip found the following timings:-
| Part No | Chip | Manufacture | Speed nS | Package | Price | |||
|---|---|---|---|---|---|---|---|---|
| Min | Typ | Max | ||||||
| 1741279 | SN74LVC2G32QDCURQ1 | Ti | <2.5 | SM8 | $ 0.55 | |||
| SN74LVC1G139DCUT | Ti / Farnell | <2.5 | VSSOP | £0.404 | ||||
The 2 input positive display or gates fast times.
Here is the chip that has been chosen:-
|
|
Full Data Sheet for SN74LVC2G32-Q1 DUAL TWO-INPUT POSITIVE-OR GATE & Timing
|
This chip provides the logic for the /CE signal.
Circuit Description
There are 2 inputs A and B. The /CE signal enables the chip.
Logic Lab Test v Truth Table
The decoder logic and OR gates were checked against the Simplified Schematic with thanks to http://www.neuroproductions.be/logic-lab/ for the simulator.
| Inputs Enable Select | Outputs | ||||||
|---|---|---|---|---|---|---|---|
| /CE | A | B | /Y3 | /Y2 | /Y1 | /Y0 | |
| 00 | 0 | 0 | 0 | 1 | 1 | 1 | 0 |
| 01 | 0 | 0 | 1 | 1 | 1 | 0 | 1 |
| 02 | 0 | 1 | 0 | 1 | 0 | 1 | 1 |
| 03 | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
| 1 | X | X | 1 | 1 | 1 | 1 | |
| /CE = 0 | /CE = 1 | |
|---|---|---|
00 |
|
|
01 |
|
|
02 |
|
|
03 |
|
|
The eight combinations all agree.
http://www.neuroproductions.be/logic-lab/index.php?id=64582
http://www.neuroproductions.be/logic-lab/index.php?id=64583
The simulator file may be used and viewed at
http://www.neuroproductions.be/logic-lab/index.php?id=64758
Circuit Diagram using a 2-to-4 Line Decoder and 2 Dual OR Chips.
To be Updated wrong circuit displayed
All the components required are fitted on a single card.
2-to-4 Line Decoder and 2 Dual OR Chips
If a full 74xx139 chip is required it can be either be
- piggy backed (using the DIL connections) to Z88 Turbo card if the 16 Pin SOIC footprint is required or
- used on its own with pins, plugged into a 16 pin DIL socket on the board where the original 74xx139 was..
Headers and Sockets
| Photo | Dia hole mm | |||
|---|---|---|---|---|
| 8 way header |
| 1.00 | http://uk.farnell.com/te-connectivity-amp/826629-8/header-1row-8way/dp/3418364 | £0.596 |
| 0.90 | http://uk.farnell.com/te-connectivity-amp/215297-8/socket-vertical-1row-8way/dp/3419101 | £0.54 |
Building the circuit on a breadboard externally
Components required
|
|
2 MSOP-8 IC adaptors were obtained in addition to the DUAL TWO-INPUT POSITIVE-OR GATE chips.
This circuit could now be bread-boarded and tested.
This photo needs to be replaced with one showing the Dual NAND gates.
The four signal and power lines can be seen connecting the card to the breadboard.
This picture needs to be replaced.
The Games play without crashing.
Oscilloscope Readings
(This picture needs replacing)
This produced the signals required.
This trace shows the Flash chip being selected (/CE1) in 3nS.
The RAM (/CE) would be the same timings.
Signals not the same abbreviations as the circuit
The names of the signals on the scope are not all the same as shown in the circuit.
| Signal | Scope | Circuit |
|---|---|---|
| A19 | A19 | A19 |
| /CE1 | _CE1 | /CE1 |
| /CE0 | _CE | /CE0 |
Printed Circuit Board
Main points
- Fast low power decoder used
- Fast low power NAND gates used
- 4 Layer board used
- All fits in a 16 DIL footprint
4 Layer Board
Signal lines are used on all 4 layers.
| Power Allocation | |
|---|---|
| top copper | GND |
| inner 1 | GND |
| inner 2 | Vcc |
| bottom | GND |
Provisional Layout
To be updated when completed
The 7 layers
Here are the layers printed on A4 sheets. The board is small, zooming in is generally helpful.
To be done