4. Z80 CPU

Owned by Elpekos
Last updated: Nov 17, 2015
4 min read

The CPU is CMOS version of the Z80 microprocessor, chosen for its low working and standby power consumption. The standby power mode is selected by the CPU whenever possible (eg when it is waiting for a keyboard input) by executing the HALT instruction. The HALT output, sensed by the gate array results in the latter stopping the 3.2768 MHz CPU clock, in turn inducing the standby power mode. Normal CPU working is resumed when the clock is restored and the gate array requests an interrupt.

The CPU has a standard three bus input/output arrangement comprising the data bus, address bus and control bus.

Data Bus. D7 - D0 constitutes an 8-bit bi-directional data bus with active high, tri-state input/outputs. It is used during keyboard scanning, for exchanges with the gate array (in particular with the memory over the memory data bus MDH-MDA) and is available on the peripheral expansion connector PL8.

Address Bus. A15 - A0 constitutes a 16-bit address bus with active high tri-state outputs. It is used to set up addresses for the gate array (in particular with the memory on memory address bus MA19 - MA0), for keyboard scanning (A15 - A8 only) and is available on the peripheral expansion connectors PLO and PL9.

Control Bus. The control bus is a collection of individual signals which generally organise the flow of data between the CPU and the gate array on the address and data buses. All signals are available on the peripheral expansion connectors and are described below:

 

    • Maskable Interrupt (INT) - active low signal generated by the gate array to call the CPU's maskable interrupt routine. As part of this routine the CPU reads the interrupt register in the gate array to determine the cause of the interrupt and therefore what action to take. Two machine states trigger this interrupt, battery low, signalled by the power supply, and the keyboard scan request. Battery low simply causes the LCD to display the BAT LOW legend, the keyboard scan request causes the CPU to scan the keyboard lines to detect whether any keys are pressed.

 

    • Non-Maskable Interrupt (NMI) - active low signal generated by the gate array to call the CPU's non-maskable interrupt routine. This routine is responsible for saving the current status of the machine prior to executing the HALT instruction. On receipt of the resultant HALT signal from the CPU the gate array induces the coma state. An NMI is generated by the gate array when the timeout set up using the panel options expires, the memory slot flap is opened or in response to the external sense signal SNS. The latter is generated in the event of a power supply failure or if a plug in memory/peripheral card is inserted/removed.

 

    • Halt (/HALT) is an active low signal generated when the CPU executes a HALT instruction. HALT can be generated autonomously by the CPU to induce the snooze state or in response to the NMI interrupt to induce the coma state.

 

    • Memory Request (/MREQ) - this signal is active low indicating when the address bus holds a valid address for a memory read/write operation.

 

    • Input/Output Request (/IORQ) - this signal is active low when the address bus holds a valid address for a gate array register read/write operation or when the CPU is scanning the keyboard.

 

    • Machine Cycle 1 (/M1) - this signal is active low when the CPU is executing the first cycle of a multi-machine cycle instruction. Using M1 the gate array can determine when the CPU is writing to memory or conducting a refresh cycle (see para. 6.6.3). The use of this signal saves a pin on the gate array which would otherwise have to receive both the CPU write (/WR) and refresh (/RFSH) signals.

 

    • The read/write signals (/RD and /WR) are active low, one or other being asserted when the CPU wants to read or write data to a memory location, or a register in the gate array. Both signals are available on the peripheral interface connector SK9; only /RD is supplied to the gate array.

 

    • Reset (/RST) - active low signal output from the gate array when the reset pushbutton SW1 is pressed. The effect of operating the reset pushbutton is discussed below.

 

  • Reset Operation. Two operations of the pushbutton are required to effect a reset, one to start the CPU clock (since for a large proportion of the time the CPU will be in the snooze state) and the second which the CPU can then act upon. The reset pulses themselves (RIN on IC4 pin 97 and /RST on IC1 pin 26) reset the circuits within the gate array and cause the CPU to effect a restart. The latter results in the CPU clearing certain internal registers and then running the restart routine. The outcome of this routine is dependent on the state of the flap input to the gate array on IC4 pin 92 which the CPU reads during an I/O read cycle. If the memory card slot flap is open (FLP high) the routine effects a hard reset clearing the RAM memory. Alternatively, if the flap is closed (FLP low) a soft reset occurs erasing only the suspended activities (see the Z88 User Guide for further details).

 

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