LYONTEK - LY62W10248ML-55LLI - SRAM, 8M, 1MX8, 2.7-5.5V, 44TSOPII

This section lists the exchange between Rakewell and LYONTEK to find out why the RAM chip fails.

This memory chip is a 'drop-in' replacement for the BSI chip (see below).

TESTED FAILS when loading a file in PipeDream.

Manufacture response:-

We have read the information on web-site provided from customer. Just as customer said, yes, the circuit diagram is pretty straightforward. We can not find an problem from that. Just we know, the major differences between our parts and BSI's are the design on ESD protection devices, shown as below. We use type 2 on our parts, but BSI uses type 1 without using P-diode,Dp. We wondered if this could be the issue. Maybe, we need to make some tests on customer's AP board to learn the real situations.

My response :-

Sorry about the delay in replying but I have been comparing the specs between both these chips and running more tests.
Where do we go from here?
I just can’t believe it is a timing issue because the Z80 is running at 3.2768 Mhz. A read or write command takes 3 clock cycles. This gives 915.52734375 nS and the device only needs 55.
How can we test and see what is happening? Have you got any suitable test equipment?

Technical Spec of a Flash and RAM chips

		Z80 4MHz	*A29040B Flash*	BS62LV8001	AS6C8008	LY62W10248-55	CY62158ELL-45ZSXI
Supply Voltage Min	V			2.4	2.7	2.7	4.5
Supply Voltage Typ	V			-	3.0	3.0	5.0
Supply Voltage Max	V			5.5	5.5	5.5	5.5
Input High Voltage	V	2.2 to VCC	0.7 x VCC min to VCC+0.3	2.2 to VCC+0.3	2.4 to VCC+0.3	2.4 to VCC+0.5	2.2 to VCC + 0.5 V
Input Low Voltage	V	-0.3 to 0.8	0.5 to 0.8	-0.5 to 0.8	- 0.2 to 0.6	- 0.2 to 0.6	–0.5 to 0.8
Output High Voltage	V	2.4 min	0.85 x VCC	2.4 min	2.4 min		2.4 min
Output Low Voltage	V	0.4 max	0.45	0.4 max	0.4 max		0.4 max
Standby Power	uA		1	3.5 to 50	6 to 80	10 to 50	2 to 8
Power Consumption	mA		20 - 40	39	60	30 to 60	1.8 to 3
VCC for Data Retention	V			1.5	2.0	1.5	2.0
Read Timings
Read Cycle Time tRC	ns		55 min	55 min	55 min	55 min	45 min
Address Access Time tAA			55 min	55 max	55 max	55 max	45 max
Chip Enable Access Time tACE			55 min	55 max	55 max	55 max	45 max
Output Enable Access Time tOE			30 max	25 max	30 max	30 max	22 max
Chip Enable to Output in Low-Z tCLZ			18 min	10 min	10 min	10 min	5 min
Output Enable to Output in Low-Z tOLZ			18 min	10 min	5 min	5 min	10 min
Chip Disable to Output in High-Z tCHZ				30 max	20 max	20 max	18 max
Output Disable to Output in High-Z tOHZ				25 max	20 max	20 max	18 max
Output Hold from Address Change tOH			0	10 min	10 min	10 min	10 min
Write Timings
Write Cycle Time tWC			55 min	55 min	55 min	55 min	45 min
Address Valid to End of Write tAW			40 min	40 min	50 min	50 min	35 min
Chip Enable to End of Write tCW				0	50 min	50 min	35 min
Address Set-up Time tAS			0	40 min	0	0	35 min
Write Pulse Width tWP			20 min	30 min	45 min	45 min	35 min
Write Recovery Time tWR			0	0	0	0
Data to Write Time Overlap tDW			25 min	25 min	25 min	25 min	25 min
Data Hold from End of Write Time tDH			0	0	0	0	0
Data Setup to Write End							25 min
Output Active from End of Write tOW				5 min	5 min	5 min
Write to Output in High-Z tWHZ				25 max	20 max	20 max	10 max
		THE Z80 CPU : TIMING