FPGA project

This project page describes the hardware specifications of the new FPGA based Z88 platform.

Project status

Full original blink implementation is done and really stable, tested during 3 continuous days without reset.

Platform is actually a common TERASIC DE-1 board with a Cyclone 2 FPGA. Implementation uses the on-board Flash EPROM and SRAM.

Serial port is wired to a FTDI serial-USB adapter. It is fully working and Eazylink, Y-modem transfers are reliable at 38K.

Screen is a VGA monitor, keyboard a standard PS2.

Coma and snooze are implemented, pressing the 2 shifts keys on the PS2 keyboards wakes-up immediately the machine and turns on the VGA monitor.

Improvements

NextZ80 CPU (done)

Working at 6.25MHz. Since this CPU works 4 times faster than the Z80, global speed is 8 times the original Z88.

Zetriz project is compiled in less than 1'30" versus 12' on the real Z88.

Serial port (done)

Full original implementation is done.

The UTEST flag in TXC enables fast baud rates up to 500K baud.

The 31.5K baud speed is possible, allowing a MIDI interface implementation.

SPI controller (done)

Two SPI controller have been implemented in the blink. One is interfaced with the SD card slot.

SPI layer is implemented
SD protocol is implemented
FAT32 is implemented in read-only
VFAT with long filename support is implemented (allowing OZ full filename length support)
TODO : SPI layer and SD layer OZ API (W.I.P.)
TODO : integration in OZ VFS (transparent virtual filesystem already used for eprom file area)
TODO : write support, erase, format...

SDRAM

The speed will be greatly improved with SDRAM usage. Speed limitation is due to Flash EPROM and SRAM chip latency.

Using a 4M SDRAM will unlock this limitation. A bootstrap has to be implemented in the CPU in order to load OZ in the first 512K before hard reset.

Read-only protection needs to be implemented in order to protect system.

Dual VGA display

Two VGA output are planned.

OZ could easily support a dual display by switching between two screen base files.

Advanced memory management unit

This feature is intend to protect OZ integrity and avoid lowram corruption. Principles are described below.

Extended Segment register will allow up to 1GByte RAM allocation without loosing compatibility with the actual 4M range.

Blink ports

New blink registers are in bold.

`Port`	`Read`	`Width`	`Write`	`Width`	`Softcopy`

`Port`	`Read`	`Width`	`Write`	`Width`	`Softcopy`

`$70`			`PB0`	`13`	`$0460, $0470`
`$71`			`PB1`	`10`	`$0461, $0471`
`$72`			`PB2`	`9`	`$0462, $0472`
`$73`			`PB3`	`11`	`$0463, $0473`
`$74`			`SBR`	`11`	`$0464, $0474`
`$75`			`SB1`	`8`	`$0475`
`$76`			`SB2`	`8`	`$0476`
`$77`	`SCI`	`16`	`SCM`	`8`	`$0477`

`$B0`	`MID`	`16`	`COM`	`8`	`$04B0`
`$B1`	`STA`	`8`	`INT`	`8`	`$04B1`
`$B2`	`KBD`	`8`	`MVP`	`16`	`$04B2`
`$B3`			`EPR`	`8`	`$04B3`
`$B4`			`TACK`	`3`	`$04B4`
`$B5`	`TSTA`	`3`	`TMK`	`3`	`$04B5`
`$B6`			`ACK`	`8`	`$04B6`
`$B7`			`ROM`	`8`	`$04B7`

`$C0`			`ES0`	`16`	`$04C0, $04D0`
`$C1`			`ES1`	`16`	`$04C1, $04D1`
`$C2`			`ES2`	`16`	`$04C2, $04D2`
`$C3`			`ES3`	`16`	`$04C3, $04D3`

`$D0`	`TIM0`	`8`	`SR0`	`8`	`$04D0`
`$D1`	`TIM1`	`6`	`SR1`	`8`	`$04D1`
`$D2`	`TIM2`	`8`	`SR2`	`8`	`$04D2`
`$D3`	`TIM3`	`8`	`SR3`	`8`	`$04D3`
`$D4`	`TIM4`	`5`

`$E0`	`RXD`
`$E1`	`RXE`	`6`
`$E2`			`RXC`	`8`	`$04E2`
`$E3`			`TXD`	`11`	`$04E3`
`$E4`			`TXC`	`8`	`$04E4`
`$E5`	`UIT`	`8`	`UMK`	`7`	`$04E5`
`$E6`			`UAK`	`7`	`$04E6`

`$F0`	`SPS0`	`8`	`SPS0`	`16`	`$04F0 (LSB), $04F1 (MSB)`
`$F1`	`SPD0`	`8`	`SPD0`	`8`
`$F2`	`SPS1`	`8`	`SPS1`	`16`	`$04F2 (LSB), $04F3 (MSB)`
`$F3`	`SPD1`	`8`	`SPD1`	`8`

Read

$77 SCI 16bits Screen Informations

$B0 MID 16bit Machine Identification

Write

$77 SCM 8bits Screen Mode ($00: 640x64 pixels, $01: 640x480 pixels)

$B7 ROM 8bits Read Only Memory (bit 0 : $00-$1F, bit 2: $40-$5F, bit 3: $60-$7F, ... bit 7 : $E0-$FF, read-only if reset)

$B2 MVP 16bits Memory Violation Protection (1bit for each page of the first 4K, read-only if reset)

$C0 ES0 16bits Extended segment 0 register (overwrites SR0)

$C1 ES1 16bits Extended segment 1 register (overwrites SR1)

$C2 ES2 16bits Extended segment 2 register (overwrites SR2)

$C3 ES3 16bits Extended segment 3 register (overwrites SR3)

Advanced Memory Management Unit

The MVP and ROM registers are intend to protect memory against system violation.

The MVP allows writing in the first 4K of bank $20. Reset, Interrupt and RST instructions set this register to $FF.

The OZ calls are allowed to write in this area, they restore this register state on exit.

Application or user code cannot write in this area, if so, an interrupt is fired and MVP flag is set in INT (MVP flag replaces A19 bit, unused).

This feature ensure a strong system stability.

The ROM register hold the Read-Only configuration of 512K areas in the first 4M range.

Bit reset stands for a read only area. Each bit cover a 512K area.

Bit 0 : $00-$1F area
Bit 1 : $20-$3F area
Bit 2 : $40-$5F area
Bit 3 : $60-$7F area
Bit 4 : $80-$9F area
Bit 5 : $A0-$BF area
Bit 6 : $C0-$DF area
Bit 7 : $E0-$1F area

Screen

Resolution

Screen resolution is set by the SCM register, mode 0, default, is the standard 640x64 pixels panel.

Mode 1, VGA, the choice of the FPGA platform.

Mode 2, WVGA, is planned since 800x480 pixels resolution are a quite common LCD available (for future portable).

The blink returns screen width and height with SCW and SCH registers.

SBF

The screen base file is held in one bank.