The Zilog Z80 CPU Instruction Set

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Last updated: Nov 20, 2017 by Paul RobertsVersion comment
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Introduction

The reference of the Z80 mnemonics have been included here for the sake of a quick guide during program analysation, optimising and debugging. For convenience, we have also attached a complete Reference User Manual of the Z80 CPU, describing all aspects; hardware organisation, detailed instruction set reference with examples, etc. 

If you want more comprehensive information, Wikipedia describes in great detail the historical aspect and the many variations of the Zilog Z80 8bit microprocessor.

Notation rules

r       specifies any one of the registers: A, B, C, D, E, H, L. 
(HL)    specifies the contents of memory at the location addressed by HL. 
n       specifies a 8 bits expression in the range (0 to 255). 
nn      specifies a 16 bits expression in the range (0 to 65535), low byte first. 
d       specifies a 8 bits displacement value in the range (-128 to 127). 
(nn)    specifies the contents of memory at the location addressed by nn address. 
b       specifies an expression in the range (0 to 7). 
e       specifies a one-byte expression in the range (-126 to 129). 
cc      specifies the condition flag : 
          Z (Zero), NZ (Not Zero) 
          C (Carry), NC (Not Carry) 
          P (Plus), M (Minus) 
          PO (Parity Odd), PE (Parity Even) 
qq      specifies any one of the register pairs: BC, DE, HL or AF. 
ss      specifies any one of the register pairs: BC, DE, HL or SP. 
pp      specifies any one of the register pairs: BC, DE, IX or SP. 
rr      specifies any one of the register pairs: BC, DE, IY or SP. 
s       specifies any of r, n, (HL), (IX+d) or (IY+d). 
dd      specifies any one of the register pairs: BC, DE, HL or SP. 
m       specifies any of r, (HL), (IX+d) or (IY+d). 

Flagregister notation:

?       Changed functionally according to operation.
*       Flag not affected.
X       Flag is set randomly by operation.
0       Flag is reset.
1       Flag is set.
V       Flag signals overflow by operation.
P       Flag signals even parity.

The symbol 'V' in the Flags column displays the P/V flag.
The leftmost flag bit, the Sign flag, represents bit 7 - the rightmost bit, the Carry flag, represents bit 0. Bit 5 and 3 (with the '.' symbol) are not used, but are set randomly by the processor during execution of various instructions.

The numbers in the instruction opcode column represents the binary representation of the byte opcode from bit 0 to 7 (total of eight bits).
When no hexadecimal number is displayed several opcodes are generated from the bit pattern.
The index registers registers IX and IY are fully represented with the IY register example (IX only varies with the 1. opcode DDh).

The following pages organises the instruction set according to their group.

Introduction

The reference of the Z80 mnemonics have been included here for the sake of a quick guide during program analysation, optimising and debugging. For convenience, we have also attached a complete Reference User Manual of the Z80 CPU, describing all aspects; hardware organisation, detailed instruction set reference with examples, etc. 

If you want more comprehensive information, Wikipedia describes in great detail the historical aspect and the many variations of the Zilog Z80 8bit microprocessor.

Notation rules

r       specifies any one of the registers: A, B, C, D, E, H, L. 
(HL)    specifies the contents of memory at the location addressed by HL. 
n       specifies a 16 bits expression in the range (0 to 255). 
nn      specifies a 8 bits expression in the range (0 to 65535), low byte first. 
d       specifies a 8 bits displacement value in the range (-128 to 127). 
(nn)    specifies the contents of memory at the location addressed by nn address. 
b       specifies an expression in the range (0 to 7). 
e       specifies a one-byte expression in the range (-126 to 129). 
cc      specifies the condition flag : 
          Z (Zero), NZ (Not Zero) 
          C (Carry), NC (Not Carry) 
          P (Plus), M (Minus) 
          PO (Parity Odd), PE (Parity Even) 
qq      specifies any one of the register pairs: BC, DE, HL or AF. 
ss      specifies any one of the register pairs: BC, DE, HL or SP. 
pp      specifies any one of the register pairs: BC, DE, IX or SP. 
rr      specifies any one of the register pairs: BC, DE, IY or SP. 
s       specifies any of r, n, (HL), (IX+d) or (IY+d). 
dd      specifies any one of the register pairs: BC, DE, HL or SP. 
m       specifies any of r, (HL), (IX+d) or (IY+d). 

Flagregister notation:

?       Changed functionally according to operation.
*       Flag not affected.
X       Flag is set randomly by operation.
0       Flag is reset.
1       Flag is set.
V       Flag signals overflow by operation.
P       Flag signals even parity.

The symbol 'V' in the Flags column displays the P/V flag.
The leftmost flag bit, the Sign flag, represents bit 7 - the rightmost bit, the Carry flag, represents bit 0. Bit 5 and 3 (with the '.' symbol) are not used, but are set randomly by the processor during execution of various instructions.

The numbers in the instruction opcode column represents the binary representation of the byte opcode from bit 0 to 7 (total of eight bits).
When no hexadecimal number is displayed several opcodes are generated from the bit pattern.
The index registers registers IX and IY are fully represented with the IY register example (IX only varies with the 1. opcode DDh).

The following pages organises the instruction set according to their group.

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